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    SOI hybrid structure with selective epitaxial growth of silicon
    2.
    发明授权
    SOI hybrid structure with selective epitaxial growth of silicon 有权

    公开(公告)号：US06555891B1

    公开(公告)日：2003-04-29

    申请号：US09690674

    申请日：2000-10-17

    申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    IPC分类号： H01L2900

    CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

    摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

    SOI hybrid structure with selective epitaxial growth of silicon
    4.
    发明授权
    SOI hybrid structure with selective epitaxial growth of silicon 失效
    具有硅选择性外延生长的SOI混合结构

    公开(公告)号：US06635543B2

    公开(公告)日：2003-10-21

    申请号：US10335652

    申请日：2002-12-31

    申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

    IPC分类号： A01L21331

    CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

    摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

    摘要翻译： 一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。 衬垫层形成在硅层上。 焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。 通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。 绝缘垫片形成在沟槽的侧壁上。 在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。 去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。 电子器件可以形成在沟槽的外延硅内。 这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。 半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。

    Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application
    5.
    发明授权
    Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application 失效
    硅抗熔丝结构，绝缘体上的体和硅绝缘体制造方法和应用

    公开(公告)号：US06396120B1

    公开(公告)日：2002-05-28

    申请号：US09527191

    申请日：2000-03-17

    申请人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

    发明人： Claude L Bertin ,  Toshiharu Furukawa ,  Erik L. Hedberg ,  Jack A. Mandelman ,  William R. Tonti ,  Richard Q. Williams

    IPC分类号： H01L2972

    CPC分类号： H01L29/78696 ,  H01L21/823412 ,  H01L21/823456 ,  H01L23/5252 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/42384 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.

    摘要翻译： 一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。 半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域 在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。 在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏 电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给 所述基板。

    Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity
    6.
    发明授权
    Structure and method for planar MOSFET DRAM cell free of wordline gate conductor to storage trench overlay sensitivity 失效
    平面MOSFET DRAM单元的结构和方法没有字线栅极导体与存储沟槽覆盖灵敏度

    公开(公告)号：US06271080B1

    公开(公告)日：2001-08-07

    申请号：US09465109

    申请日：1999-12-16

    申请人： Jack A. Mandelman ,  Toshiharu Furukawa ,  William R. Tonti

    发明人： Jack A. Mandelman ,  Toshiharu Furukawa ,  William R. Tonti

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867 ,  H01L27/10861 ,  H01L27/10873

    摘要： A memory cell (8F2 and sub-8F2) formed by: (a) forming a stack of at least four material layers on a surface of a semiconductor substrate, wherein at least two of said material layers of said stack are selectively etchable relative to each other; (b) patternwise etching through said stack to define a critical pattern of remaining stack and spaces where said semiconductor substrate is exposed, said critical pattern defining possible locations for trench capacitors and gate conductors; (c) filling said spaces with a filler material which is selectively etchable relative to a topmost layer of said remaining stack; (d) planarizing the filler material stopping at said topmost layer of said remaining stack; (e) forming trench capacitors in said semiconductor substrate by etching through portions of said filler material and said substrate, wherein said etching removes a portion of said topmost layer of said remaining stack and exposes a portion of a layer of said stack that is next to the topmost layer; (f) planarizing the remaining portion of said stack and filler material to remove the remaining portion of the topmost layer of said stack and the remaining portion of the layer that is next to the topmost layer and thereby exposing a layer of said stack that is second from the topmost layer; (g) replacing at least a portion of either said remaining stack and/or remaining filler material with a placeholder material corresponding to locations for gate conductors; and (h) forming said gate conductors and remaining portions of said transistors, bitlines and wordlines of said memory cell.

    摘要翻译： 通过以下步骤形成的存储器单元（8F2和sub-8F2）：（a）在半导体衬底的表面上形成至少四个材料层的堆叠，其中所述堆叠的至少两个所述材料层相对于每个 其他; （b）通过所述堆叠进行图案蚀刻以限定所述半导体衬底暴露的剩余堆叠和空间的临界图案，所述临界图案限定了沟槽电容器和栅极导体的可能位置; （c）用相对于所述剩余堆叠的最上层选择性地蚀刻的填充材料填充所述空间; （d）使在所述剩余堆叠的所述最上层停止的填充材料平坦化; （e）通过蚀刻穿过所述填充材料和所述衬底的部分在所述半导体衬底中形成沟槽电容器，其中所述蚀刻去除所述剩余堆叠的所述最上层的一部分，并且暴露所述堆叠层的下一部分的一部分 最上层; （f）使所述堆叠和填充材料的剩余部分平坦化，以去除所述堆叠的最上层的剩余部分和邻近最上层的层的剩余部分，从而暴露出第二层的所述堆叠层 从最上层; （g）用对应于栅极导体的位置的占位符材料代替所述剩余堆叠和/或剩余填充材料的至少一部分; 和（h）形成所述晶体管的所述栅极导体和剩余部分，所述存储单元的位线和字线。

    TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT
    8.
    发明申请
    TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT 有权
    用于可编程集成电路的抗融合结构

    公开(公告)号：US20100230781A1

    公开(公告)日：2010-09-16

    申请号：US12537473

    申请日：2009-08-07

    申请人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger A. Booth, JR. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L23/525 ,  H01L21/768

    CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.

    摘要翻译： 沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。 反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层 沟槽的侧壁。 电介质层设置在导电插塞和掺杂区域之间。 电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。 沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。

    Electrically programmable π-shaped fuse structures and methods of fabrication thereof
    9.
    发明授权
    Electrically programmable π-shaped fuse structures and methods of fabrication thereof 失效
    电气可编程的pi形熔丝结构及其制造方法

    公开(公告)号：US07656005B2

    公开(公告)日：2010-02-02

    申请号：US11768254

    申请日：2007-06-26

    申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

    摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和 在第二支撑件上方的第二端子部分。 保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。 第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
    10.
    发明授权
    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
    具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上

    公开(公告)号：US07545253B2

    公开(公告)日：2009-06-09

    申请号：US12128100

    申请日：2008-05-28

    申请人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01H85/08 ,  H01L23/62

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

    摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.

    摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。