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公开(公告)号：US07906390B2
公开(公告)日：2011-03-15
申请号：US11780519
申请日：2007-07-20
IPC分类号： H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.
摘要翻译： 一种CMOS器件及其形成方法。 所述器件包括形成在半导体衬底中的源极和漏极，所述源极和漏极由衬底的沟道区分隔开; 形成在基板的顶表面上的栅极电介质和形成在栅极电介质层的顶表面上的非常薄的金属或金属合金栅电极，与栅电极邻接并与之电接触的多晶硅线，多晶硅线比 栅电极。 该方法包括：通过在沟道区域上方形成沟槽并将金属沉积到沟槽中形成栅电极。
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公开(公告)号：US20090020827A1
公开(公告)日：2009-01-22
申请号：US11780519
申请日：2007-07-20
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/66545 , H01L21/28194 , H01L29/4958 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/6659
摘要： A CMOS device and method of forming the CMOS device. The device including a source and a drain formed in a semiconductor substrate, the source and the drain and separated by a channel region of the substrate; a gate dielectric formed on a top surface of the substrate and a very thin metal or metal alloy gate electrode formed on a top surface of the gate dielectric layer, a polysilicon line abutting and in electrical contact with the gate electrode, the polysilicon line thicker than the gate electrode. The method including, forming the gate electrode by forming a trench above the channel region and depositing metal into the trench.
摘要翻译： 一种CMOS器件及其形成方法。 所述器件包括形成在半导体衬底中的源极和漏极，所述源极和漏极由衬底的沟道区分隔开; 形成在基板的顶表面上的栅极电介质和形成在栅极电介质层的顶表面上的非常薄的金属或金属合金栅电极，与栅电极邻接并与之电接触的多晶硅线，多晶硅线比 栅电极。 该方法包括：通过在沟道区域上方形成沟槽并将金属沉积到沟槽中形成栅电极。
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3.发明申请公开(公告)号：US20090001481A1
公开(公告)日：2009-01-01
申请号：US11768270
申请日：2007-06-26
申请人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
发明人： Ethan Harrison Cannon , Toshiharu Furukawa , David Vaclav Horak , Jack A. Mandelman , William Robert Tonti
IPC分类号： H01L27/105 , H01L21/8238
CPC分类号： H01L27/0733 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L28/40
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes (a) a semiconductor substrate, (b) a shallow trench isolation (STI) region on the semiconductor substrate, and (c) a first semiconductor transistor on the semiconductor substrate. The first semiconductor transistor includes (I) a first source/drain region, (ii) a second source/drain region, and (iii) a first gate electrode region. The first and second source/drain regions are doped with a same doping polarity. The semiconductor structure further includes a first doped region in the semiconductor substrate. The first doped region is on a first side wall and a bottom wall of the STI region. The first doped region is in direct physical contact with the second source/drain region. The first doped region and the second source/drain region are doped with a same doping polarity.
摘要翻译： 半导体结构及其形成方法。 半导体结构包括（a）半导体衬底，（b）半导体衬底上的浅沟槽隔离（STI）区域，以及（c）半导体衬底上的第一半导体晶体管。 第一半导体晶体管包括（I）第一源极/漏极区域，（ii）第二源极/漏极区域，以及（iii）第一栅极电极区域。 第一和第二源/漏区掺杂相同的掺杂极性。 半导体结构还包括在半导体衬底中的第一掺杂区域。 第一掺杂区域位于STI区域的第一侧壁和底壁上。 第一掺杂区域与第二源极/漏极区域直接物理接触。 第一掺杂区域和第二源极/漏极区域掺杂相同的掺杂极性。
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公开(公告)号：US5937289A
公开(公告)日：1999-08-10
申请号：US3106
申请日：1998-01-06
申请人： Gary Bela Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William Robert Tonti
发明人： Gary Bela Bronner , Jeffrey P. Gambino , Jack A. Mandelman , Carl J. Radens , William Robert Tonti
IPC分类号： H01L21/225 , H01L21/28 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L21/8238
CPC分类号： H01L21/28035 , H01L21/82345
摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.
摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选定数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，其中各个栅极结构在其顶部部分上包含自对准的绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。
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公开(公告)号：US08008713B2
公开(公告)日：2011-08-30
申请号：US12410935
申请日：2009-03-25
IPC分类号： H01L29/00
CPC分类号： H01L29/792 , H01L21/26586 , H01L27/115 , H01L27/11568 , H01L29/7926
摘要： A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
摘要翻译： 提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元，其允许将致密的非易失性随机存取 基于SOI的互补金属氧化物半导体（CMOS）技术的存储器（NVRAM）单元。 使用常规沟槽处理处理沟槽，并且在本发明方法的开始附近处理允许将存储单元的制造完全从SOI逻辑处理分离开来的处理。
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6.发明授权公开(公告)号：US07804148B2
公开(公告)日：2010-09-28
申请号：US11355799
申请日：2006-02-16
IPC分类号： H01L23/58 , H01L31/058 , H01L31/02 , H01L31/0232 , H01L31/024 , H01L21/033 , H01L21/00
CPC分类号： H01L21/268 , H01L21/84 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： An opto-thermal annealing mask stack layer includes a thermal dissipative layer located over a substrate. A reflective layer is located upon the thermal dissipative layer. A transparent capping layer, that may have a thickness from about 10 to about 100 angstroms, is located upon the reflective layer. The opto-thermal annealing mask layer may be used as a gate electrode within a field effect device.
摘要翻译： 光热退火掩模层叠层包括位于衬底上的散热层。 反射层位于热耗散层上。 可以具有约10至约100埃厚度的透明覆盖层位于反射层上。 光热退火掩模层可以用作场效应器件中的栅电极。
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公开(公告)号：US20100230781A1
公开(公告)日：2010-09-16
申请号：US12537473
申请日：2009-08-07
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate.
摘要翻译： 沟槽反熔丝结构，设计结构体现在用于设计，制造或测试可编程集成电路的机器可读介质中。 反熔丝结构包括具有延伸到衬底中的多个侧壁的沟槽，靠近沟槽侧壁的衬底的半导体材料中的掺杂区域，沟槽中的导电插塞以及沟槽中的介电层 沟槽的侧壁。 电介质层设置在导电插塞和掺杂区域之间。 电介质层被配置为使得施加在掺杂区域和导电插塞之间的编程电压导致沟槽区域内的电介质层的击穿。 沟槽侧壁布置成具有与深沟槽的底壁和基板的顶表面之间的位置无关的横截面几何形状。
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公开(公告)号：US07790530B2
公开(公告)日：2010-09-07
申请号：US12254960
申请日：2008-10-21
IPC分类号： H01L21/00
CPC分类号： H01L27/108 , H01L27/10829 , H01L27/10867 , H01L27/1203
摘要： A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
摘要翻译： 使用绝缘体上硅（SOI）CMOS技术制造用于制造致密（20或18平方）布局的DRAM存储单元和工艺顺序。 具体地，本发明提供了与现有SOI CMOS技术兼容的致密的高性能SRAM单元替换。 各种增益单元布局在本领域中是已知的。 本发明通过提供利用SOI CMOS制造的致密布局来改善现有技术的状态。 通常，存储单元包括分别设置有栅极，源极和漏极的第一晶体管; 分别具有第一栅极，第二栅极，源极和漏极的第二晶体管; 以及具有第一端子的电容器，其中所述电容器的第一端子和所述第二晶体管的第二栅极包括单个实体。
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9.发明授权Electrically programmable π-shaped fuse structures and methods of fabrication thereof 失效电气可编程的pi形熔丝结构及其制造方法公开(公告)号：US07656005B2
公开(公告)日：2010-02-02
申请号：US11768254
申请日：2007-06-26
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.
摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和 在第二支撑件上方的第二端子部分。 保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。 第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。
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10.发明授权Memory cells with planar FETs and vertical FETs with a region only in upper region of a trench and methods of making and using same 有权具有平面FET的存储单元和仅在沟槽的上部区域中的区域的垂直FET，以及制造和使用它们的方法公开(公告)号：US07642588B2
公开(公告)日：2010-01-05
申请号：US11259296
申请日：2005-10-26
申请人： Kangguo Cheng , Jack A. Mandelman
发明人： Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L27/10841 , G11C11/403 , G11C11/405 , H01L27/0207 , H01L27/10864 , H01L27/10894 , H01L29/045
摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell of a substrate that includes (1) a PFET with an orientation approximately planar to a surface of the substrate; and (2) an NFET coupled to the approximately planar PFET. An orientation of the NFET in the substrate is approximately perpendicular to the orientation of the PFET. Numerous other aspects are provided.
摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是基板的存储单元，其包括（1）具有与基板的表面近似平面的取向的PFET; 和（2）耦合到大致平面PFET的NFET。 衬底中NFET的取向近似垂直于PFET的取向。 提供了许多其他方面。
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