公开(公告)号：US08299591B2

公开(公告)日：2012-10-30

申请号：US12347005

申请日：2008-12-31

申请人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon ,  Dong You Kim ,  Ki Bon Cha

发明人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon ,  Dong You Kim ,  Ki Bon Cha

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 半导体芯片设置在第一区域中并且电连接到各个布线，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US08024857B2

公开(公告)日：2011-09-27

申请号：US12347161

申请日：2008-12-31

申请人： Young Hy Jung ,  Jae Sung Oh ,  Ki Il Moon ,  Ki Chae Kim ,  Chan Sun Lee ,  Jin Ho Gwon ,  Jae Youn Choi

发明人： Young Hy Jung ,  Jae Sung Oh ,  Ki Il Moon ,  Ki Chae Kim ,  Chan Sun Lee ,  Jin Ho Gwon ,  Jae Youn Choi

IPC分类号： H05K3/02 ,  H05K1/02 ,  H05K1/03 ,  H01L21/00 ,  H01L23/13

CPC分类号： H01L23/13 ,  H01L23/538 ,  H01L23/562 ,  H01L2924/0002 ,  Y10T29/49155 ,  H01L2924/00

摘要： A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.

摘要翻译： 提出了一种具有防止或最小化失真的加强构件的半导体封装的衬底。 用于半导体封装的衬底包括衬底主体，绝缘层和加强构件。 基板主体具有第一区域，具有多个芯片安装区域，沿着第一区域的周边设置的第二区域，设置在每个芯片安装区域中的电路图案和沿着第二区域布置的虚设图案。 绝缘层覆盖第一和第二区域，并且具有暴露每个电路图案的一部分的开口。 加强构件设置在第二区域中并防止基板主体的偏转。

公开(公告)号：US07732903B2

公开(公告)日：2010-06-08

申请号：US11760182

申请日：2007-06-08

申请人： Jae Sung Oh

发明人： Jae Sung Oh

IPC分类号： H01L23/02

CPC分类号： H05K1/147 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/10159 ,  H05K2201/10537 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00

摘要： A memory module includes a module substrate and a plurality of package units mounted to the module substrate such that they partially overlap each other. Each package unit has at least one memory semiconductor package attached thereto. Each package unit includes a flexible substrate, which has outer terminals provided over a lower surface adjacent to one edge thereof to form electrical connections with the module substrate, and the memory semiconductor package attached to one surface or each of both upper and lower surfaces of the flexible substrate.

摘要翻译： 存储器模块包括模块基板和安装到模块基板的多个封装单元，使得它们部分地彼此重叠。 每个封装单元具有至少一个连接到其上的存储器半导体封装。 每个封装单元包括柔性基板，其具有设置在与其一个边缘相邻的下表面上的外部端子，以形成与模块基板的电连接，并且存储器半导体封装件附接到所述模块基板的一个表面或两个上表面和下表面中的每一个 柔性基材。