公开(公告)号：US20100072598A1

公开(公告)日：2010-03-25

申请号：US12347005

申请日：2008-12-31

申请人： Jae Sung OH ,  Moon Un HYUN ,  Jong Hyun KIM ,  Jin Ho Gwon ,  Dong You KIM ,  Ki Bon CHA

发明人： Jae Sung OH ,  Moon Un HYUN ,  Jong Hyun KIM ,  Jin Ho Gwon ,  Dong You KIM ,  Ki Bon CHA

IPC分类号： H01L23/538 ,  H01L23/48

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 半导体芯片设置在第一区域中并且电连接到各个布线，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US5977643A

公开(公告)日：1999-11-02

申请号：US877566

申请日：1997-06-17

申请人： Joong Ha You ,  Ki Bon Cha

发明人： Joong Ha You ,  Ki Bon Cha

IPC分类号： H01L23/28 ,  H01L21/56 ,  H01L21/60 ,  H01L21/607 ,  H01L23/12 ,  H01L23/29 ,  H01L23/48 ,  H01L23/495 ,  H01L23/58

CPC分类号： H01L24/85 ,  H01L23/293 ,  H01L24/78 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/73215 ,  H01L2224/78 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181

摘要： A chip-size semiconductor package and fabrication method is provided that reduces the size of the package. Further, the electrical path from the chip pads to the external leads is reduced to improve electrical characteristics. In addition, the external leads can be formed directly at the location of the chip pads. The chip-size semiconductor package has a passivation film is formed on a semiconductor chip excluding the chip pads thereon. Inner ends of conductive wires are vertically coupled to corresponding chip pads, respectively. Then, the semiconductor chip is sealed with a molding resin excluding the outer ends of the conductive wires that protrude. The outer ends can be formed as external leads having a shape, such as circular external balls, based on the intended use.

摘要翻译： 提供了减小封装尺寸的芯片尺寸半导体封装和制造方法。 此外，减小了从芯片焊盘到外部引线的电路，以改善电气特性。 此外，外部引线可以直接形成在芯片焊盘的位置。 芯片尺寸的半导体封装在半导体芯片上形成除了芯片焊盘之外的钝化膜。 导线的内端分别垂直耦合到相应的芯片焊盘。 然后，除了突出的导线的外端之外，用模制树脂密封半导体芯片。 根据预期用途，外端可以形成为具有诸如圆形外球的形状的外部引线。

公开(公告)号：US08299591B2

公开(公告)日：2012-10-30

申请号：US12347005

申请日：2008-12-31

申请人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon ,  Dong You Kim ,  Ki Bon Cha

发明人： Jae Sung Oh ,  Moon Un Hyun ,  Jong Hyun Kim ,  Jin Ho Gwon ,  Dong You Kim ,  Ki Bon Cha

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L21/67346 ,  H01L23/3128 ,  H01L23/32 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5384 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/08111 ,  H01L2224/16225 ,  H01L2224/29009 ,  H01L2224/29011 ,  H01L2224/32146 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01087

摘要： A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

摘要翻译： 半导体封装包括具有第一区域的基板主体的基板，围绕第一区域限定的第二区域和围绕第二区域限定的第三区域。 布线被放置在基板主体上，并且布线具有延伸到第三区域的第一端。 连接图案被放置在第三区域中并且电连接到布线的第一端。 半导体芯片设置在第一区域中并且电连接到各个布线，并且模制构件设置在第一和第二区域中并且覆盖半导体芯片。

公开(公告)号：US07291906B2

公开(公告)日：2007-11-06

申请号：US10745566

申请日：2003-12-29

申请人： Ki Bon Cha ,  Dong You Kim

发明人： Ki Bon Cha ,  Dong You Kim

IPC分类号： H01L23/42 ,  H01L23/58 ,  H01L23/02

CPC分类号： H01L23/5387 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/85 ,  H01L2225/06527 ,  H01L2225/06558 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1082 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/0401

摘要： Disclosed are a stack package and a fabricating method thereof using a ball grid array semiconductor package (hereinafter, referred to as “BGA PKG”). The stack package can easily electrically connect the stacked BGA PKGs with each other by simplifying a stack structure between the BGA PKGs, and increase bonding reliability by improving bonding force bonded portions of solder balls of substrates.

摘要翻译： 公开了使用球栅阵列半导体封装（以下称为“BGA PKG”）的堆叠封装及其制造方法。 通过简化BGA PKG之间的堆叠结构，堆叠封装可以容易地将堆叠的BGA PKG电连接，并且通过改善衬底的焊球的接合力结合部分来提高焊接可靠性。

公开(公告)号：US06924556B2

公开(公告)日：2005-08-02

申请号：US10279977

申请日：2002-10-25

申请人： Ki Bon Cha

发明人： Ki Bon Cha

IPC分类号： H01L23/28 ,  B23K1/00 ,  H01L25/10 ,  H01L29/40

CPC分类号： B23K1/0016 ,  B23K2101/40 ,  H01L25/105 ,  H01L2224/32245 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/01079 ,  H01L2924/14

摘要： Disclosed are a stack package and a method of manufacturing the same, which has improved electrical properties by virtue of a reduced signal line length, and also allows reduction of production costs of the stack package. The stack package of the present invention includes panels having an area for mounting respective CSP packages and pin-shaped connectors. The panels include circuit patterns for electrical connection to the CSP packages, which are formed at portions of the panels corresponding to the CSP packages to be mounted. Also, the panels have first openings for electrical connection to the circuit patterns, which are formed at both sides of the circuit patterns. The pin-shaped connectors are inserted through the first openings of the panels. The panels are stacked in at least two layers in such a manner that the first openings of one panel correspond to the first openings of the other panels, so that the connectors are electrically connected to the circuit patterns of the stacked panels.

摘要翻译： 公开了一种堆叠封装及其制造方法，其通过减小的信号线长度而具有改进的电性能，并且还允许降低堆叠封装的生产成本。 本发明的堆叠包括具有用于安装各个CSP封装和针形连接器的区域的面板。 这些面板包括用于电连接到CSP封装的电路图案，其形成在与要安装的CSP封装相对应的面板的部分处。 此外，面板具有用于电连接到电路图案的第一开口，其形成在电路图案的两侧。 销形连接器插入板的第一开口。 面板以至少两层堆叠，使得一个面板的第一开口对应于另一个面板的第一开口，使得连接器电连接到堆叠面板的电路图案。

公开(公告)号：US20080203552A1

公开(公告)日：2008-08-28

申请号：US10570208

申请日：2005-03-08

申请人： Dong You Kim ,  Ki Bon Cha

发明人： Dong You Kim ,  Ki Bon Cha

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/05599

摘要： Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is mounted on the other face of the circuit board. A signal connection member is provided for transmitting signals of the first BGA package and the second BGA package to each other. The second BGA package is provided with a signal connection pad. One end of the signal connection member is bonded to the signal connection pad and the other end of the signal connection member is bonded to the circuit pattern of the circuit board. A method of fabricating the stacked package is also disclosed.

摘要翻译： 这里公开了堆叠式包装。 堆叠封装包括第一BGA封装和第二BGA封装中的两个或更多个和具有电路图案的电路板。 第一个BGA封装安装在电路板的一个面上，第二个BGA封装安装在电路板的另一个面上。 提供信号连接构件，用于将第一BGA封装和第二BGA封装的信号彼此传输。 第二个BGA封装配有信号连接板。 信号连接部件的一端接合到信号连接焊盘，信号连接部件的另一端接合到电路板的电路图案上。 还公开了一种制造堆叠封装的方法。