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公开(公告)号：US4978594A
公开(公告)日：1990-12-18
申请号：US258530
申请日：1988-10-17
申请人： James A. Bruce , Michael L. Kerbaugh , Ranee W. Kwong , Tanya N. Lee , Harold G. Linde , Harbans S. Sachdev
发明人： James A. Bruce , Michael L. Kerbaugh , Ranee W. Kwong , Tanya N. Lee , Harold G. Linde , Harbans S. Sachdev
IPC分类号： H01L21/302 , G03F7/09 , G03F7/40 , H01L21/027 , H01L21/3065
摘要： A process for forming a pattern on a substrate utilizing photolithographic techniques. In this process a layer of polymeric material containing a fluorine-containing compound is applied over the substrate and cured. A layer of photoresist material is applied over the polymeric material imagewise exposed and developed to reveal the image on the underlying polymeric material. Thereafter, the photoresist is silylated, and the structure is reactive ion etched to transfer the pattern to the underlying substrate. The fluorine component provides an underlying structure free of residue and cracking.
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公开(公告)号：US07492941B2
公开(公告)日：2009-02-17
申请号：US11769431
申请日：2007-06-27
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
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公开(公告)号：US06338921B1
公开(公告)日：2002-01-15
申请号：US09479150
申请日：2000-01-07
IPC分类号： G03F102
CPC分类号： G03F7/0035 , G03F1/36
摘要： A mask (50′) with linewidth compensation and a method of making same. The mask provides for optimized imaging of isolated patterns (64) and nested patterns (70) present on the same mask. The compensated mask is formed from an uncompensated mask (50) and comprises an upper surface (56) upon which the isolated and nested patterns are formed. The isolated pattern comprises a first segment (76) having first sidewalls (76S). The nested pattern comprises second segments (72) proximate each other and having second sidewalls (72S). A partial conformal layer (86) covers the first segment and has feet (90) outwardly extending a distance d from the first sidewalls along the upper surface. The feet are preferably of a thickness that partially transmits exposure light.
摘要翻译： 具有线宽补偿的掩模（50'）及其制造方法。 掩模提供对同一掩模上存在的孤立图案（64）和嵌套图案（70）的优化成像。 补偿掩模由未补偿的掩模（50）形成，并且包括形成隔离和嵌套图案的上表面（56）。 隔离图案包括具有第一侧壁（76S）的第一段（76）。 嵌套图案包括彼此靠近并具有第二侧壁（72S）的第二段（72）。 部分保形层（86）覆盖第一段并且具有沿着上表面向外延伸距离第一侧壁的距离d的脚（90）。 脚部优选地具有部分地透射曝光光的厚度。
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4.发明授权Method of photolithographically defining three regions with one mask step and self aligned isolation structure formed thereby 失效用一个掩模步骤和由此形成的自对准隔离结构光刻地限定三个区域的方法
公开(公告)号：US6147394A
公开(公告)日：2000-11-14
申请号：US172366
申请日：1998-10-14
IPC分类号： G03F7/004 , G03F1/00 , G03F7/095 , G03F7/20 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/76 , H01L21/762 , H01L29/00
CPC分类号： G03F7/70633 , G03F7/095 , G03F7/2022 , G03F7/2024 , H01L21/0274 , H01L21/762
摘要： The preferred embodiment of the present invention provides a method for defining three regions on a semiconductor substrate using a single masking step. The preferred embodiment uses a photoresist material having, simultaneously, both a positive tone and a negative tone response to exposure. This combination of materials can provide a new type of resist, which we call a hybrid resist. The hybrid resist comprises a positive tone component which acts at a first actinic energy level and a negative tone component which acts at a second actinic energy level, with the first and second actinic energy levels being separated by an intermediate range of actinic energy. When hybrid resist is exposed to actinic energy, areas of the resist which are subject to a full exposure cross link to form a negative tone line pattern, areas which are unexposed form remain photoactive and form a positive tone pattern, and areas which are exposed to intermediate amounts of radiation become soluble and wash away during development. This exposes a first region on the mask. By then blanket exposing the hybrid resist, the positive tone patterns become soluble and will wash away during development. This exposes a second region on the mask, with the third region still be covered by the hybrid resist. Thus, the preferred embodiment is able to define three regions using a single masking step, with no chance for overlay errors.
摘要翻译： 本发明的优选实施例提供了一种使用单个掩蔽步骤在半导体衬底上限定三个区域的方法。 优选实施例使用光刻胶材料，同时具有曝光的正色调和负色调响应。 这种材料的组合可以提供一种新型的抗蚀剂，我们称之为混合抗蚀剂。 混合抗蚀剂包含作用于第一光化能级的正色调成分和以第二光化能级起作用的负色调成分，其中第一和第二光化能级被光化能的中间范围分隔。 当混合抗蚀剂暴露于光化能时，受到完全曝光的抗蚀剂的区域交联以形成负色调线图案，未曝光形式的区域保持光活性并形成正色调图案，并且暴露于 中间量的辐射在开发过程中变得可溶并被冲走。 这暴露了掩码上的第一个区域。 然后毯子暴露混合抗蚀剂，正色调图案变得可溶，并且在显影过程中将被洗掉。 这掩盖了掩模上的第二区域，第三区域仍被混合抗蚀剂覆盖。 因此，优选实施例能够使用单个掩蔽步骤来定义三个区域，而不会叠加错误。
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公开(公告)号：US07492940B2
公开(公告)日：2009-02-17
申请号：US11761856
申请日：2007-06-12
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定何时发生了给定掩模层上的缺陷。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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公开(公告)号：US07269808B2
公开(公告)日：2007-09-11
申请号：US10908786
申请日：2005-05-26
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A design verification method, including (a) providing in a design a design electrically conducting line and a design contact region being in direct physical contact with the design electrically conducting line; (b) modeling a simulated electrically conducting line of the design electrically conducting line; (c) simulating a possible contact region of the design contact region, wherein the design contact region and the possible contact region are not identical; and (d) determining that the design electrically conducting line and the design contact region are potentially defective if an interfacing surface area of the simulated electrically conducting line and the possible contact region is less than a pre-specified value.
摘要翻译： 一种设计验证方法，包括（a）在设计中提供与设计导电线直接物理接触的设计导电线和设计接触区; （b）对设计导电线的模拟导电线进行建模; （c）模拟设计接触区域的可能的接触区域，其中设计接触区域和可能的接触区域不相同; 以及（d）如果所述模拟导电线路和所述可能接触区域的接口表面积小于预定值，则确定所述设计导电线路和所述设计接触区域具有潜在的缺陷。
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公开(公告)号：US06395624B1
公开(公告)日：2002-05-28
申请号：US09253952
申请日：1999-02-22
申请人： James A. Bruce , Randy W. Mann
发明人： James A. Bruce , Randy W. Mann
IPC分类号： H01L21336
CPC分类号： H01L21/223 , H01L21/268 , Y10S438/952
摘要： The present invention provides a novel method of forming implants with Projection Gas-Immersion Laser Doping (PGILD) process that overcomes the disadvantages of the prior art methods. In particular, the preferred method applies a reflective coating over features before the application of the PGILD laser. The reflective coating lowers the amount of heat absorbed by the features, improving the reliability of the fabrication process. The preferred method is particularly applicable to the fabrication of field effect transistors (FETs). In this application, a gate stack is formed, and a reflective coating is over the gate stack. An anti-reflective coating (ARC) is then applied over the reflective coating. The anti-reflective coating reduces variability of the photolithographic process used to pattern the gate stack. After the gate stack is patterned, the anti-reflective coating is removed, leaving the reflective coating on the gate stack. The PGILD process can then be used to form source/drain doped regions on the transistors. The reflective coating reduces the amount of heat absorbed by the gate stack, and thus provides an improved method for fabricating transistors.
摘要翻译： 本发明提供了一种克服现有技术方法的缺点的用投影气体浸渍激光掺杂（PGILD）工艺形成植入物的新方法。 特别地，优选的方法在施加PGILD激光器之前对反射涂层施加特征。 反射涂层降低了由特征吸收的热量，提高了制造工艺的可靠性。 优选的方法特别适用于场效应晶体管（FET）的制造。 在这种应用中，形成栅极叠层，并且反射涂层在栅极叠层上方。 然后将抗反射涂层（ARC）涂覆在反射涂层上。 抗反射涂层降低了用于对栅极堆叠进行图案化的光刻工艺的变化。 在栅极堆叠被图案化之后，去除抗反射涂层，使反射涂层留在栅极叠层上。 然后可以使用PGILD工艺在晶体管上形成源极/漏极掺杂区域。 反射涂层减少了栅叠层吸收的热量，因此提供了一种制造晶体管的改进方法。
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公开(公告)号：US06369397B1
公开(公告)日：2002-04-09
申请号：US09225120
申请日：1999-01-04
IPC分类号： G01N1310
CPC分类号： H01J37/3045 , H01J37/3174 , H01J2237/3175 , Y10S977/85
摘要： A method and apparatus for positioning a wafer in an electron beam lithography system. This method includes the steps of positioning a scanned probe microscope in the lithography system, and determining the distance between a preset location on the scanned probe microscope and a reference position in the lithography system. The wafer is brought into physical contact with that preset location, and then the wafer is moved a predetermined distance from the preset location on order to position the wafer at the desired focal plane in the lithography system.
摘要翻译： 一种用于在电子束光刻系统中定位晶片的方法和装置。 该方法包括以下步骤：将扫描的探针显微镜放置在光刻系统中，以及确定扫描的探针显微镜上的预设位置与光刻系统中的参考位置之间的距离。 将晶片与该预设位置物理接触，然后将晶片从预置位置移动预定距离，以将晶片定位在光刻系统中所需的焦平面处。
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公开(公告)号：US20110061030A1
公开(公告)日：2011-03-10
申请号：US12555219
申请日：2009-09-08
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.
摘要翻译： 公开了用于验证光掩模设计的解决方案。 在一个实施例中，验证光掩模设计的方法包括：使用多个掩模形状和用于初始半导体制造工艺的变化模型来模拟初始半导体制造工艺，以生成用于初始半导体制造工艺的多个轮廓; 使用用于初始半导体制造工艺的轮廓和随后的半导体制造工艺的变型模型来模拟随后的半导体制造工艺，以生成用于后续半导体制造工艺的多个轮廓; 使用多个轮廓重复模拟至少一个随后的半导体制造工艺，用于随后的半导体制造工艺和用于后续半导体制造工艺的变型模型; 以及在计算机可读存储介质上生成和存储光掩模设计的验证结果。
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公开(公告)号：US07257247B2
公开(公告)日：2007-08-14
申请号：US09683836
申请日：2002-02-21
申请人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
发明人： James A. Bruce , Orest Bula , Edward W. Conrad , William C. Leipold , Michael S. Hibbs , Joshua J. Krueger
IPC分类号： G06K9/00
CPC分类号： G03F1/84
摘要： An automated system for analyzing mask defects in a semiconductor manufacturing process is presented. This system combines results from an inspection tool and design layout data from a design data repository corresponding to each mask layer being inspected with a computer program and a predetermined rule set to determine when a defect on a given mask layer has occurred. Mask inspection results include the presence, location and type (clear or opaque) of defects. Ultimately, a determination is made as to whether to scrap, repair or accept a given mask based on whether the defect would be likely to cause product failure. Application of the defect inspection data to the design layout data for each mask layer being inspected prevents otherwise acceptable wafer masks from being scrapped when the identified defects are not in critical areas of the mask.
摘要翻译： 提出了一种用于分析半导体制造过程中的掩模缺陷的自动化系统。 该系统将来自检查工具的结果和来自被检查的每个掩模层的设计数据存储库的设计布局数据与计算机程序和预定规则集相结合，以确定给定掩模层上的缺陷何时发生。 掩模检查结果包括缺陷的存在，位置和类型（透明或不透明）。 最终，根据缺陷是否可能导致产品故障，确定是否废除，修理或接受给定的掩模。 将缺陷检查数据应用于被检查的每个掩模层的设计布局数据防止当所识别的缺陷不在掩模的关键区域时被报废。
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