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1.发明授权Memory system having synchronous-link DRAM (SLDRAM) devices and controller 失效具有同步链路DRAM（SLDRAM）器件和控制器的存储器系统公开(公告)号：US06442644B1
公开(公告)日：2002-08-27
申请号：US09132158
申请日：1998-08-10
申请人： David B. Gustavson , David V. James , Hans A. Wiggers , Peter B. Gillingham , Cormac M. O'Connell , Bruce Millar , Jean Crepeau , Kevin J. Ryan , Terry R. Lee , Brent Keeth , Troy A. Manning , Donald N. North , Desi Rhoden , Henry Stracovsky , Yoshikazu Morooka
发明人： David B. Gustavson , David V. James , Hans A. Wiggers , Peter B. Gillingham , Cormac M. O'Connell , Bruce Millar , Jean Crepeau , Kevin J. Ryan , Terry R. Lee , Brent Keeth , Troy A. Manning , Donald N. North , Desi Rhoden , Henry Stracovsky , Yoshikazu Morooka
IPC分类号： G06F1200
CPC分类号： G11C7/1066 , G06F13/409 , G06F13/4243 , G11C7/10 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C2207/2254 , H05K1/0219 , H05K1/0246 , H05K2201/0715 , H05K2201/09236 , H05K2201/09254 , H05K2201/09309 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689 , Y02D10/14 , Y02D10/151
摘要： A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.
摘要翻译： SLDRAM系统配备有多个在线可校准存储器模块和用于向存储器模块发出单播和多播命令分组的存储器控制器。 命令分组通过单向命令链路发送，该单向命令链路包括一对互补的命令时钟线，命令FLAG线和多个未实现的命令位线。 每个命令时钟线，命令位线和FLAG线都是SLIO传输线。 响应于一个或多个双向数据链路上的命令分组执行数据传送操作，每个双向数据链路包括两对互补的数据时钟线对，以及多个未实现的数据位线。 每个数据时钟线和数据位线都是SLIO传输线。 每个SLIO传输线都是单端端接的，最好采用短截线电阻。
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公开(公告)号：US5935263A
公开(公告)日：1999-08-10
申请号：US886195
申请日：1997-07-01
申请人： Brent Keeth , Troy A. Manning , Chris G. Martin , Kim M. Pierce , Wallace E. Fister , Kevin J. Ryan , Terry R. Lee , Mike Pearson , Thomas W. Voshell
发明人： Brent Keeth , Troy A. Manning , Chris G. Martin , Kim M. Pierce , Wallace E. Fister , Kevin J. Ryan , Terry R. Lee , Mike Pearson , Thomas W. Voshell
CPC分类号： H03M13/093 , G11C29/38 , G11C29/48
摘要： A memory device includes an output data path that transfers data from an I/O circuit coupled to a memory array to an output tri-state buffer. A comparing circuit compares data from the I/O circuit to a desired data pattern. If the data does not match the desired pattern, the comparing circuit outputs an error signal that is input to the output buffer. When the output buffer receives the error signal, the output buffer is disabled and outputs a tri-state condition on a data bus. Since the error signal corresponds to more than one data bit, the tri-state condition of the output buffer is held for more than one tick of the data clock, rather than only a single tick. Consequently, the tri-state condition remains on the bus for sufficiently long that a test system can detect the tri-state condition even at very high clock frequencies.
摘要翻译： 存储器件包括将数据从耦合到存储器阵列的I / O电路传送到输出三态缓冲器的输出数据路径。 比较电路将来自I / O电路的数据与期望的数据模式进行比较。 如果数据与所需模式不匹配，则比较电路输出输入到输出缓冲器的错误信号。 当输出缓冲器接收到错误信号时，输出缓冲器被禁止，并在数据总线上输出三态条件。 由于误差信号对应于多个数据位，所以输出缓冲器的三态条件保持数据时钟的多于一个刻度，而不是仅一个刻度。 因此，三态条件保持在总线上足够长，使得测试系统即使在非常高的时钟频率也可以检测三态条件。
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公开(公告)号：US06658523B2
公开(公告)日：2003-12-02
申请号：US09804221
申请日：2001-03-13
IPC分类号： G06F1200
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
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公开(公告)号：US06851016B2
公开(公告)日：2005-02-01
申请号：US10720183
申请日：2003-11-25
IPC分类号： G06F12/00 , G11C7/10 , G11C7/22 , G11C11/407
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
摘要翻译： 在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。 本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统 读延迟。
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5.发明申请Method and system for using dynamic random access memory as cache memory 有权使用动态随机存取存储器作为高速缓冲存储器的方法和系统公开(公告)号：US20080177943A1
公开(公告)日：2008-07-24
申请号：US12069812
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。
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6.发明授权公开(公告)号：US07027349B2
公开(公告)日：2006-04-11
申请号：US10969177
申请日：2004-10-21
申请人： Kevin J. Ryan , Brent Keeth
发明人： Kevin J. Ryan , Brent Keeth
IPC分类号： G11C8/00
CPC分类号： G11C8/12
摘要： A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection signals. A memory controller transmits bank select signals over bank select signal lines and encoded chip select signals on the command and address bus which are used to select an individual memory device or group of memory devices in a bank for an operation.
摘要翻译： 提供了一种方法和装置，用于使用专门的存储体选择信号与编码的芯片选择信号结合来选择存储器系统中的存储器件或一组存储器件。 存储器控制器通过存储体选择信号线发送存储体选择信号，并在命令和地址总线上传送编码的芯片选择信号，这些信号用于选择用于操作的存储体中的各个存储器件或存储器组组。
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公开(公告)号：US06535450B1
公开(公告)日：2003-03-18
申请号：US09640759
申请日：2000-08-18
申请人： Kevin J. Ryan , Brent Keeth
发明人： Kevin J. Ryan , Brent Keeth
IPC分类号： G11C800
CPC分类号： G11C8/12
摘要： A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection signals. A memory controller transmits bank select signals over bank select signal lines and encoded chip select signals on the command and address bus which are used to select an individual memory device or group of memory devices in a bank for an operation.
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公开(公告)号：US06948027B2
公开(公告)日：2005-09-20
申请号：US10815877
申请日：2004-03-30
IPC分类号： G11C7/10 , G11C11/406 , G11C11/409 , G11C15/04 , G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
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9.发明授权Method and system for using dynamic random access memory as cache memory 有权使用动态随机存取存储器作为高速缓冲存储器的方法和系统公开(公告)号：US07917692B2
公开(公告)日：2011-03-29
申请号：US12069812
申请日：2008-02-12
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0846 , G06F12/0897 , G11C7/1006 , G11C7/1042 , G11C11/406 , G11C11/409 , G11C15/043
摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.
摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。
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公开(公告)号：US06842393B2
公开(公告)日：2005-01-11
申请号：US10302964
申请日：2002-11-25
申请人： Kevin J. Ryan , Brent Keeth
发明人： Kevin J. Ryan , Brent Keeth
CPC分类号： G11C8/12
摘要： A method and apparatus is provided for selecting a memory device or a group of memory devices in a memory system using dedicated bank select signals in combination with encoded chip selection signals. A memory controller transmits bank select signals over bank select signal lines and encoded chip select signals on the command and address bus which are used to select an individual memory device or group of memory devices in a bank for an operation.
摘要翻译： 提供了一种方法和装置，用于使用专门的存储体选择信号与编码的芯片选择信号结合来选择存储器系统中的存储器件或一组存储器件。 存储器控制器通过存储体选择信号线发送存储体选择信号，并在命令和地址总线上传送编码的芯片选择信号，这些信号用于选择用于操作的存储体中的各个存储器件或存储器组组。
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