公开(公告)号：US06355530B1

公开(公告)日：2002-03-12

申请号：US09630867

申请日：2000-08-02

Applicant: James Ho ,  Cheng-Hui Chung ,  Chen-Bin Lin

Inventor： James Ho ,  Cheng-Hui Chung ,  Chen-Bin Lin

IPC: H01L218236

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method of manufacturing a mask ROM. A sacrificial silicon oxide layer is formed on the active region upon the substrate. Patterning the sacrificial silicon oxide layer in order to form a plurality of parallel openings, thereby exposing a portion of the active region. A polysilicon layer is formed on the openings and openings are formed thereon. An ion implantation process is performed on the polysilicon layer. Using a thermal flow process, the ions within the polysilicon layer are driven through the openings into the lower portion of the substrate, thereby forming an ion doping region. The polysilicon layer is etchbacked until the sacrificial silicon oxide layer is exposed. The sacrificial silicon oxide layer is removed.

Abstract translation: 一种制造掩模ROM的方法。 在衬底上的有源区上形成牺牲氧化硅层。 对牺牲氧化硅层进行成形以便形成多个平行的开口，从而暴露一部分有源区。 在开口上形成多晶硅层，在其上形成开口。 在多晶硅层上进行离子注入工艺。 使用热流程，多晶硅层内的离子通过开口被驱动到衬底的下部，从而形成离子掺杂区域。 蚀刻多晶硅层直到牺牲氧化硅层露出。 去除牺牲氧化硅层。

公开(公告)号：US06225209B1

公开(公告)日：2001-05-01

申请号：US09150525

申请日：1998-09-10

Applicant: Yei-Hsiung Lin ,  Chih-Chun Huang ,  Chen-Bin Lin ,  Cheng-Hui Chung

Inventor： Yei-Hsiung Lin ,  Chih-Chun Huang ,  Chen-Bin Lin ,  Cheng-Hui Chung

IPC: H01L214763

CPC classification number: H01L21/02126 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/665

Abstract: A method for fabricating a crack resistant inter-layer dielectric for a salicide process. The method includes forming an insulating layer on a provided substrate, forming a planarized inter-layer dielectric layer on the insulating layer, and performing a short-duration thermal treatment to increase the density of the inter-layer dielectric layer.

Abstract translation: 一种用于制造用于自对准硅化物工艺的耐裂纹层间电介质的方法。 该方法包括在所提供的衬底上形成绝缘层，在绝缘层上形成平坦化的层间电介质层，并进行短时间热处理以增加层间电介质层的密度。

公开(公告)号：US06242315B1

公开(公告)日：2001-06-05

申请号：US09186126

申请日：1998-11-04

Applicant: Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

Inventor： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

IPC: H01L2120

CPC classification number: H01L28/55 ,  H01L21/76838 ,  H01L28/60

Abstract: A method of manufacturing the metallic electrodes of a capacitor in a mixed mode semiconductor device. The method comprises the steps of providing a substrate having a conductive layer and the lower electrode of a capacitor formed thereon, and then depositing a dielectric layer over the substrate. A first opening and a second opening are then formed in the dielectric layer. The first opening exposes a portion of the conductive layer while the second opening exposes a portion of the lower electrode. Finally, a conductive plug and the upper electrode of the capacitor are formed in the respective first and second openings that are in corresponding positions above the conductive layer and lower electrode, respectively.

Abstract translation: 一种在混合模式半导体器件中制造电容器的金属电极的方法。 该方法包括以下步骤：提供具有导电层和形成在其上的电容器的下电极的衬底，然后在衬底上沉积介电层。 然后在电介质层中形成第一开口和第二开口。 第一开口暴露导电层的一部分，而第二开口暴露下部电极的一部分。 最后，分别在导电层和下电极上方的相应位置的相应的第一和第二开口中形成导电插塞和电容器的上电极。

公开(公告)号：US6086951A

公开(公告)日：2000-07-11

申请号：US332342

申请日：1999-06-14

Applicant: Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

Inventor： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L28/55 ,  H01L28/60 ,  H01L21/76801 ,  H01L21/76838

Abstract: A method of forming metallic capacitor. The method includes forming a lower electrode for forming the capacitor and a metal conductive line over an inter-layer dielectric such that there are gaps between and on the sides of the lower electrode and the metal conductive line. Thereafter, a first oxide layer is formed that fills the gap, and then a second oxide layer is formed over the inter-layer dielectric. The second oxide layer is later patterned to form a cap oxide layer having an opening that exposes a portion of the lower electrode. Subsequently, a thin dielectric layer is formed over the lower electrode and the cap oxide layer. Finally, an upper electrode is formed over the thin dielectric layer filling the opening.

Abstract translation: 一种形成金属电容器的方法。 该方法包括形成用于形成电容器的下电极和在层间电介质上的金属导电线，使得在下电极和金属导线之间的两侧之间和之间存在间隙。 此后，形成填充间隙的第一氧化物层，然后在层间电介质上形成第二氧化物层。 随后将第二氧化物层图案化以形成具有暴露下部电极的一部分的开口的帽氧化物层。 随后，在下电极和盖氧化物层上形成薄介电层。 最后，在填充开口的薄介电层上形成上电极。

公开(公告)号：US6033965A

公开(公告)日：2000-03-07

申请号：US363074

申请日：1999-07-28

Applicant: Chen-Bin Lin ,  Feng-Ming Liu ,  James Ho ,  Yu-Ju Liu

Inventor： Chen-Bin Lin ,  Feng-Ming Liu ,  James Ho ,  Yu-Ju Liu

IPC: H01L27/06 ,  H01L21/20 ,  H01L21/8242

CPC classification number: H01L27/0629

Abstract: A process for fabricating a mixed signal integrated circuit on a substrate, wherein the substrate is partially covered with a field oxide layer. An oxide layer is formed over a portion of the substrate, wherein the portion of the substrate is not covered with the field oxide layer. First impurities are implanted into the substrate, wherein the first impurities damage the oxide layer. A buffer layer is formed over the oxide layer. A polysilicon layer is formed over the buffer layer. Second impurities are implanted into the polysilicon layer, wherein the buffer layer prevents the oxide layer form being damaged by the second impurities. The polysilicon layer is etched to remove the polysilicon layer, wherein the buffer layer prevents the oxide layer and the substrate from being etched. The portion of buffer layer and the damaged oxide layer over the substrate are removed. The gate oxide layer is formed over the substrate.

Abstract translation: 一种在衬底上制造混合信号集成电路的工艺，其中衬底部分被场氧化物层覆盖。 在衬底的一部分上形成氧化物层，其中衬底的部分未被场氧化物层覆盖。 第一杂质被注入到基底中，其中第一杂质破坏氧化物层。 在氧化物层上形成缓冲层。 在缓冲层上形成多晶硅层。 将第二杂质注入到多晶硅层中，其中缓冲层防止氧化物层形式被第二杂质损坏。 蚀刻多晶硅层以除去多晶硅层，其中缓冲层防止氧化物层和衬底被蚀刻。 去除衬底上的缓冲层部分和损坏的氧化物层。 栅极氧化层形成在衬底上。

公开(公告)号：US6114196A

公开(公告)日：2000-09-05

申请号：US227959

申请日：1999-01-11

Applicant: Yei-Hsiung Lin ,  Chen-Bin Lin ,  Yu-Ju Liu ,  Chin-Chun Huang

Inventor： Yei-Hsiung Lin ,  Chen-Bin Lin ,  Yu-Ju Liu ,  Chin-Chun Huang

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/31

CPC classification number: H01L29/4925 ,  H01L21/28035 ,  H01L29/6659

Abstract: A method of fabricating a MOS transistor. An undoped multi-layer stacked polysilicon structure is formed on a gate oxide layer and then being doped to increase conductivity. After that, the multi-layer stacked polysilicon structure and the gate oxide layer are patterned to form a gate electrode. A source/drain region is formed by ion implantation with the gate electrode as a mask.

Abstract translation: 一种制造MOS晶体管的方法。 在栅极氧化层上形成未掺杂的多层堆叠多晶硅结构，然后掺杂以增加导电性。 之后，对多层堆叠多晶硅结构和栅氧化层进行构图以形成栅电极。 源极/漏极区域通过离子注入形成，栅电极作为掩模。

公开(公告)号：US06607951B2

公开(公告)日：2003-08-19

申请号：US09893140

申请日：2001-06-26

Applicant: Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

Inventor： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC: H01L2100

CPC classification number: H01L27/14643 ,  H01L27/14687

Abstract: A fabrication method for a CMOS image sensory device is described. An isolation layer is formed in the substrate to isolate a photodiode sensory region and a transistor device region. A gate structure is further formed on the transistor device region, followed by forming concurrently a source/drain region in the transistor device region beside the side of the gate structure and a doped region in the photodiode sensory region. Thereafter, a self-aligned block is formed on the photodiode sensory region, followed by forming a protective layer on the substrate.

公开(公告)号：US06506619B2

公开(公告)日：2003-01-14

申请号：US10104707

申请日：2002-03-25

Applicant: Chong-Yao Chen ,  Chen-Bin Lin

Inventor： Chong-Yao Chen ,  Chen-Bin Lin

IPC: H01L2100

CPC classification number: H01L27/14689 ,  H01L27/14609

Abstract: A method of fabricating CMOS image sensor. On a substrate, an isolation layer is formed to partition the substrate into a photodiode sensing region and a transistor element region. Next, on the transistor element region, a gate electrode structure is formed and then, a source/drain region is formed at the transistor element region of the two lateral sides of the gate electrode structure. At the same time, a doping region is formed on the photodiode sensing region. After that, a self-aligned barrier layer is formed on the photodiode sensing region and a protective layer is formed on the substrate. Then, a dielectric layer and a metallic conductive wire are successively formed on the protective layer. Again, a protective layer is formed on the dielectric layer and the metallic conductive wire, wherein the numbers of the dielectric layers and the metallic conductive wire depend on the fabrication process. A protective layer is formed between every dielectric layer.

Abstract translation: 一种制造CMOS图像传感器的方法。 在衬底上形成隔离层以将衬底分隔成光电二极管感测区域和晶体管元件区域。 接着，在晶体管元件区域上形成栅电极结构，然后在栅电极结构的两个侧面的晶体管元件区域形成源/漏区。 同时，在光电二极管感测区域上形成掺杂区域。 之后，在光电二极管感测区域上形成自对准势垒层，在衬底上形成保护层。 然后，在保护层上依次形成电介质层和金属导电线。 再次，在电介质层和金属导线上形成保护层，其中介电层和金属导线的数量取决于制造工艺。 在每个介电层之间形成保护层。

公开(公告)号：US06617189B1

公开(公告)日：2003-09-09

申请号：US10063949

申请日：2002-05-28

Applicant: Tze-Jing Chen ,  Ching-Chung Chen ,  Tung-Hu Lin ,  Chen-Bin Lin ,  Chi-Rong Lin

Inventor： Tze-Jing Chen ,  Ching-Chung Chen ,  Tung-Hu Lin ,  Chen-Bin Lin ,  Chi-Rong Lin

IPC: H01L2100

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14627

Abstract: A method of fabricating an image sensor on a semiconductor substrate including a sensor array region is introduced. First, an R/G/B color filter array (CFA) is formed on portions of the semiconductor substrate corresponding to the sensor array region. Then, a spacer layer is formed on the R/G/B CFA, and a plurality of U-lens is formed on the spacer layer corresponding to the R/G/B CFA. Afterwards, a buffer layer is coated to fill a space between the U-lens, and a low-temperature passivation layer is deposited on the buffer layer and the U-lens at a temperature of about 300° C. or less to prevent the R/G/B CFA from damage.

Abstract translation: 引入了在包括传感器阵列区域的半导体衬底上制造图像传感器的方法。 首先，在对应于传感器阵列区域的半导体衬底的部分上形成R / G / B滤色器阵列（CFA）。 然后，在R / G / B CFA上形成间隔层，在对应于R / G / B CFA的间隔层上形成多个U型透镜。 然后，涂覆缓冲层以填充U型透镜之间的空间，并且在约300℃或更低的温度下在缓冲层和U型透镜上沉积低温钝化层以防止R / G / B CFA从损坏。

公开(公告)号：US06541329B1

公开(公告)日：2003-04-01

申请号：US09682477

申请日：2001-09-07

Applicant: Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

Inventor： Chong-Yao Chen ,  Chen-Bin Lin ,  Feng-Ming Liu

IPC: H01L218234

CPC classification number: H01L27/14609 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689

Abstract: A plurality of active pixel sensors are formed on the surface of a semiconductor wafer. The semiconductor wafer comprises a P-type substrate, an active pixel sensor region and a periphery circuit region. A first active pixel sensor block mask (APSB mask) is formed to cover the active pixel sensor region, then at least one N-well on the surface of the semiconductor wafer not covered by the first APSB mask is formed. A second APSB mask and at least one N-well mask are formed to cover the active pixel sensor region and the region outside the P-well region. At least one P-well on the surface of the semiconductor wafer not covered by the second APSB mask and the N-well mask is formed. Finally, at least one photodiode and at least one complementary metal-oxide semiconductor (CMOS) transistor are formed on the surface of the active pixel sensor region.

Abstract translation: 在半导体晶片的表面上形成多个有源像素传感器。 半导体晶片包括P型衬底，有源像素传感器区域和外围电路区域。 形成第一有源像素传感器块掩模（APSB掩模）以覆盖有源像素传感器区域，然后形成未被第一APSB掩模覆盖的半导体晶片的表面上的至少一个N阱。 形成第二APSB掩模和至少一个N阱掩模以覆盖有源像素传感器区域和P阱区域外的区域。 形成未被第二APSB掩模和N阱掩模覆盖的半导体晶片的表面上的至少一个P阱。 最后，在有源像素传感器区域的表面上形成至少一个光电二极管和至少一个互补金属氧化物半导体（CMOS）晶体管。