公开(公告)号：US4978626A

公开(公告)日：1990-12-18

申请号：US240013

申请日：1988-09-02

申请人： Stephen S. Poon ,  James R. Pfiester ,  Frank K. Baker ,  Jeffrey L. Klein

发明人： Stephen S. Poon ,  James R. Pfiester ,  Frank K. Baker ,  Jeffrey L. Klein

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823828 ,  H01L29/78 ,  H01L29/7836 ,  H01L27/0928

摘要： An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

摘要翻译： 通过使用确保栅极氧化物层不会被无意蚀刻而不被静电电荷破裂的工艺形成LDD晶体管。 在半导体衬底之上的栅极氧化物层上形成具有不同掺杂水平的至少两个厚度的栅电极材料。 使用化学蚀刻，其中通过监测化学蚀刻反应的化学产品和化学反应物的比例，可以容易地检测到栅电极材料的蚀刻中的特定端点。 在离子注入期间允许一小层栅电极材料保留在栅极氧化物层上方，并且在制造LDD晶体管时形成和去除栅极侧壁间隔物。 在形成大多数LDD晶体管之后，去除栅电极材料的剩余保护厚度，暴露的栅极氧化层暴露于最后的氧化退火步骤。 在其他形式中，形成逆T栅极结构LDD晶体管，并且通过具有减少数量的离子注入步骤的工艺形成LDD晶体管。

公开(公告)号：US4852062A

公开(公告)日：1989-07-25

申请号：US101875

申请日：1987-09-28

申请人： Frank K. Baker ,  James R. Pfiester ,  Charles F. Hart

发明人： Frank K. Baker ,  James R. Pfiester ,  Charles F. Hart

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  G11C16/0491 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11543 ,  H01L29/7885

摘要： An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

摘要翻译： 具有浮动栅极和控制栅极的可擦除可编程只读存储器（EPROM）单元，其中浮置栅极和控制栅极与衬底中的源极/漏极/漏极/源极区域有意地偏移或不对称。 在编程期间，源极区域是与栅极间隔开的区域，而漏极区域与栅极对准。 该方向产生高栅极电流以提供更快的编程。 在读取操作期间，对准区域现在变为源极，并且间隔开的区域变为漏极以提供用于快速访问的高漏极电流。 本发明的非对称EPROM单元可以使用传统的间隔技术容易地制成。

公开(公告)号：US4811066A

公开(公告)日：1989-03-07

申请号：US109658

申请日：1987-10-19

申请人： James R. Pfiester ,  Frank K. Baker

发明人： James R. Pfiester ,  Frank K. Baker

IPC分类号： H01L29/49 ,  H01L29/48 ,  G11C11/34

CPC分类号： H01L29/4983 ,  Y10S257/903

摘要： A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi-state FET device. This device would have two different threshold voltages (V.sub.T), one where the central portion would turn on first, followed by the edges for the entire gate width to be active to give a second level of current flow. Such devices would be useful in building very compact or high density multi-state read-only-memories (ROMs).

摘要翻译： 一种紧凑的多态场效应晶体管（FET）单元，其具有栅极，该栅极具有与栅极的中心部分不同的导电类型的边缘部分。 边缘部分和中心部分都从多态FET器件的源极延伸到漏极。 该装置将具有两个不同的阈值电压（VT），其中中心部分首先接通，然后是使整个栅极宽度的边缘有效以产生第二电流。 这样的设备在构建非常紧凑或高密度多状态只读存储器（ROM）中将是有用的。

公开(公告)号：US5082794A

公开(公告)日：1992-01-21

申请号：US569097

申请日：1990-08-17

申请人： James R. Pfiester ,  Frank K. Baker ,  Richard D. Sivan

发明人： James R. Pfiester ,  Frank K. Baker ,  Richard D. Sivan

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66583 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/66553 ,  H01L29/7836 ,  H01L29/66537 ,  Y10S148/122

摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results ina formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 该结构可以用作导致形成由一次侧壁间隔物形成的逆T晶体管或常规LDD结构的工艺的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。

公开(公告)号：US4984042A

公开(公告)日：1991-01-08

申请号：US309589

申请日：1989-02-13

申请人： James R. Pfiester ,  Frank K. Baker ,  Richard D. Sivan

发明人： James R. Pfiester ,  Frank K. Baker ,  Richard D. Sivan

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66583 ,  H01L29/1045 ,  H01L29/66553 ,  H01L29/7836 ,  H01L29/66537

摘要： In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

摘要翻译： 在形成轻掺杂漏极（LDD）晶体管时，首先在有源区上的栅极氧化物上形成薄的多晶硅层。 沉积掩模层并选择性地蚀刻以暴露多晶硅层的中间部分。 这种结构可以用作导致逆T晶体管或由一次性侧壁间隔物形成的常规LDD结构的过程的一部分。 多晶硅层的暴露的中间部分用于通过选择性多晶硅沉积形成多晶硅栅极。 暴露的中间部分可以被植入用于沟道植入，从而提供对源/漏植入物的自对准。 侧壁间隔件可以形成在暴露部分内部以减小通道长度。 这些侧壁间隔物可以是氮化物以在侧壁间隔物和方便使用的低温氧化物（LTO）掩模之间提供蚀刻选择性。

公开(公告)号：US5352631A

公开(公告)日：1994-10-04

申请号：US991801

申请日：1992-12-16

申请人： Arkalgud R. Sitaram ,  James R. Pfiester

发明人： Arkalgud R. Sitaram ,  James R. Pfiester

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/336 ,  H01L21/283

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L21/2257 ,  H01L29/66545

摘要： A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

摘要翻译： 用于形成晶体管（10）的工艺通过提供衬底（12）开始。 场氧化物区域（14）或等效隔离形成在衬底（12）之上或之内。 形成栅极氧化物（16）和导电层（18）。 形成覆盖导电层（18）的掩模层（20）。 蚀刻掩模层（20）和导电层（18）以形成栅电极并限定漏区（19）和源极区（21）。 隔板（22）形成在栅电极附近。 在源极和漏极区（分别为21和19）上形成第一硅化区（26）。 掩模层防止栅电极硅化。 去除掩模层（20），并且形成覆盖栅电极的第二硅化区域（30）。 第二硅化物区域（30）和硅化物区域（26）由不同的硅化物制成。

公开(公告)号：US5319232A

公开(公告)日：1994-06-07

申请号：US76488

申请日：1993-06-14

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/225 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/66287 ,  H01L29/66492 ,  H01L29/6653 ,  Y10S257/90

摘要： A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

摘要翻译： 一种晶体管（10或11）及其形成方法。 晶体管（10）具有基板（12）。 衬底（12）具有覆盖在电介质层（14）上的上覆电介质层（14）和绝缘导电控制电极（16）。 电介质区域（18）覆盖绝缘导电控制电极（16），电介质区域（20）与绝缘导电控制电极（16）相邻。 间隔物（30）与电介质区域（20）相邻。 外延区域（24）与间隔物（30）相邻，并且间隔物（30）覆盖外延区域（24）的部分。 电介质区域（26）覆盖在外延区域（24）上。 高掺杂源极和漏极区域（32）位于外延区域（24）的下面。 位于间隔物（30）下方的LDD区域（28）与源区和漏区（32）相邻并电连接。

公开(公告)号：US5166084A

公开(公告)日：1992-11-24

申请号：US753512

申请日：1991-09-03

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/306 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/6675 ,  H01L21/30604 ,  H01L29/66772 ,  H01L29/78648 ,  Y10S148/15

摘要： A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

摘要翻译： 一种用于制造绝缘体上硅绝缘体（SOI）场效应晶体管（FET）（10,11,13,15）的工艺。 SOI FET在衬底材料（12）上制成。 在一种形式中，被称为栅极（24）的第一控制电极被包含在介电层（14）下面的衬底（12）内。 被称为栅极（26）的第二控制电极覆盖在电介质层（28）上。 源极和漏极电流电极由锗 - 硅层（18）形成。 硅层（16）形成SOI FET的隔离沟道区。 栅极（12,24）通过栅极电介质层（14,28）与沟道分离。 锗硅层（18）比制成薄以提供薄沟道区的硅层（16）厚得多。 可选的氮化物层20覆盖锗硅层（18）。

公开(公告)号：US5047812A

公开(公告)日：1991-09-10

申请号：US315668

申请日：1989-02-27

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/28132 ,  H01L29/4236

摘要： An insulated gate field effect device is disclosed having a channel region which includes both a horizontal and a vertical portion. The device is fabricated on a semiconductor substrate having a recess formed in its surface. The recess has a bottom forming a second surface with the wall of the recess extending between the first and second surfaces. A source region is formed at the first surface and a drain is formed at the second surface spaced apart from the wall. A channel region is defined along the wall and the second surface between the drain region and the source region. A gate insulator and gate electrode overlie the channel region.

摘要翻译： 公开了一种绝缘栅场效应器件，其具有包括水平和垂直部分的沟道区域。 该器件制造在具有在其表面上形成的凹部的半导体衬底上。 凹部具有形成第二表面的底部，凹部的壁在第一和第二表面之间延伸。 源区域形成在第一表面处，并且在与壁间隔开的第二表面处形成漏极。 沿着壁和漏极区域和源极区域之间的第二表面限定沟道区域。 栅极绝缘体和栅极电极覆盖沟道区域。

公开(公告)号：US5024959A

公开(公告)日：1991-06-18

申请号：US412059

申请日：1989-09-25

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/78 ,  H01L27/0928

摘要： An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region. The only lithography step needed in this portion of the process is one to protect the dopant source layer over the second region while sidewall spacers are being formed in the first region.

摘要翻译： 公开了一种使用减少数量的处理步骤的改进的LDD CMOS制造。 根据本发明的一个实施例，提供了具有相反导电类型的第一和第二表面区域的硅衬底。 第一和第二硅栅电极分别覆盖在第一和第二表面区域上。 包含第一导电类型的掺杂剂杂质的掺杂剂源层沉积在第一和第二栅电极上。 该掺杂剂源层被图案化以在第一硅栅电极的边缘处形成侧壁间隔物。 这些侧壁间隔物用于在形成于第一表面区域的器件上形成LDD结构。 在去除侧壁间隔物之后，加热结构以将掺杂剂杂质从掺杂剂源层扩散到第二表面区域中，以形成在该区域中形成的晶体管的源极和漏极区域。 在该方法的该部分中所需的唯一光刻步骤是在第二区域保护掺杂剂源层，同时在第一区域中形成侧壁间隔物的步骤。