摘要:
Provided are FeRAM device constructions and fabrication methods that provide for the direct connection of metal patterns to ferroelectric capacitors. The FeRAM device constructions utilize a combination of one or more barrier layers incorporated in conductive plugs, barrier layers incorporated in primary conductive patterns or conductive patterns formed using one or more noble metals to suppress parametric drift associated with conventional FeRAM constructions.
摘要:
A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.
摘要:
A method of fabricating a ferroelectric device includes forming a ferroelectric layer on a substrate in a reaction chamber. An inactive gas is provided into the reaction chamber while unloading the substrate therefrom to thereby substantially inhibit formation of an impurity layer on the ferroelectric layer.
摘要:
A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
摘要:
In a ferroelectric structure after a first lower electrode film is formed using a first metal nitride, a second lower electrode film is formed on the first lower electrode film using a first metal, a second metal oxide and/or a first alloy. After a ferroelectric layer is formed on the second lower electrode film, a first upper electrode film is formed on the ferroelectric layer using a second alloy. Related devices are also disclosed.
摘要:
A ferroelectric capacitor structure can include a ferroelectric layer on a lower electrode and an upper electrode on the ferroelectric layer, the upper electrode including a metal oxide and a metal.
摘要:
Disclosed are methods of forming ferroelectric material layers introducing a plurality of metallorganic source compounds into the reaction chamber, the source compounds being supplied in an appropriate ratio for forming the ferroelectric material. These metallorganic source compounds are, in turn, reacted with a NyOx/O2 oxidant gas mixture in which the NyOxcomponent(s) represents at least 50 volume percent of the oxidant gas. This mixture of metallorganic source compounds and oxidant gas mixture(s) are maintained at a deposition temperature and deposition pressure within the reaction chamber suitable for causing a reaction between the metallorganic source compounds and the oxidant gas for a deposition period sufficient to form the ferroelectric material layer. The resulting ferroelectric material layers exhibit improved uniformity, for example, near the interface with the bottom electrode.
摘要翻译:公开了形成将多个金属有机源化合物引入反应室的铁电材料层的方法,以适当的比例供给源化合物以形成铁电体材料。 这些金属有机源化合物又与N 2 O 2 O 2 / O 2 O 2氧化剂气体混合物反应,其中N“ y O x分量代表氧化剂气体的至少50体积%。 金属有机源化合物和氧化剂气体混合物的混合物保持在反应室内的沉积温度和沉积压力,适于在金属有机源化合物和氧化剂气体之间产生足以形成铁电材料的沉积时间 层。 所得到的铁电材料层表现出改善的均匀性,例如在与底部电极的界面附近。
摘要:
A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.
摘要:
A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.
摘要:
A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns on the active regions. A string select gate line may extend transversely across the active regions in parallel with the word lines. A ground select gate line may extend transversely across the active regions in parallel with the word lines.