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    Semiconductor devices and methods of fabricating semiconductor devices
    1.
    发明授权
    Semiconductor devices and methods of fabricating semiconductor devices 有权
    半导体器件和制造半导体器件的方法

    公开(公告)号：US09184174B2

    公开(公告)日：2015-11-10

    申请号：US14155649

    申请日：2014-01-15

    申请人： Jang-Gn Yun ,  Hongsoo Kim ,  Aaron Park ,  Hoosung Cho

    发明人： Jang-Gn Yun ,  Hongsoo Kim ,  Aaron Park ,  Hoosung Cho

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.

    摘要翻译： 提供半导体器件。 半导体器件可以包括衬底和衬底上的多条线。 半导体器件可以包括在衬底上并与多条线相邻的电介质层。 该半导体器件可以包括介电层中的连接元件。 在一些实施例中，半导体器件可以包括连接元件上的多个触点，以及在连接元件上的多个触点中的一个触点上以及与连接元件间隔开的触点上的导电互连。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES
    2.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES 有权
    半导体器件和制造半导体器件的方法

    公开(公告)号：US20140197542A1

    公开(公告)日：2014-07-17

    申请号：US14155649

    申请日：2014-01-15

    申请人： Jang-Gn Yun ,  Hongsoo Kim ,  Aaron Park ,  Hoosung Cho

    发明人： Jang-Gn Yun ,  Hongsoo Kim ,  Aaron Park ,  Hoosung Cho

    IPC分类号： H01L23/528

    CPC分类号： H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.

    摘要翻译： 提供半导体器件。 半导体器件可以包括衬底和衬底上的多条线。 半导体器件可以包括在衬底上并与多条线相邻的电介质层。 该半导体器件可以包括介电层中的连接元件。 在一些实施例中，半导体器件可以包括连接元件上的多个触点，以及在连接元件上的多个触点中的一个触点上以及与连接元件间隔开的触点上的导电互连。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150084204A1

    公开(公告)日：2015-03-26

    申请号：US14313031

    申请日：2014-06-24

    申请人： Jang-Gn Yun ,  Jaesun Yun ,  Hoosung Cho

    发明人： Jang-Gn Yun ,  Jaesun Yun ,  Hoosung Cho

    IPC分类号： H01L27/112 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76895 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a semiconductor device and a method of fabricating the same. The device may include a substrate including a cell array region and a peripheral circuit region, stacks on the cell array region of the substrate, the stacks having a first height and extending along a direction, a common source structure disposed between adjacent ones of the stacks, a peripheral logic structure disposed on the peripheral circuit region of the substrate and having a second height smaller than the first height, a plurality of upper interconnection lines disposed on the peripheral logic structure and extending parallel to each other, and a interconnection structure disposed between the peripheral logic structure and the upper interconnection lines, when viewed in vertical section, and electrically connected to at least two of the upper interconnection lines.

    摘要翻译： 提供半导体器件及其制造方法。 该器件可以包括包括单元阵列区域和外围电路区域的衬底，堆叠在衬底的单元阵列区域上，堆叠具有第一高度并沿着方向延伸，布置在相邻堆叠之间的公共源结构 ，设置在所述基板的外围电路区域上并且具有小于所述第一高度的第二高度的外围逻辑结构，设置在所述外围逻辑结构上并且彼此平行延伸的多个上部互连线，以及布置在 周边逻辑结构和上互连线，当从垂直截面看时，并且电连接到至少两个上互连线。

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130020647A1

    公开(公告)日：2013-01-24

    申请号：US13540799

    申请日：2012-07-03

    申请人： Sung-Min HWANG ,  In-Wook Oh ,  Woonkyung Lee ,  Aaron Park ,  Hoosung Cho

    发明人： Sung-Min HWANG ,  In-Wook Oh ,  Woonkyung Lee ,  Aaron Park ,  Hoosung Cho

    IPC分类号： H01L29/78 ,  H01L23/498

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

    摘要： Semiconductor devices are provided. The semiconductor device includes conductive patterns vertically stacked on a substrate to be spaced apart from each other, and pad patterns electrically connected to respective ones of the conductive patterns. Each of the pad patterns includes a flat portion extending from an end of the conductive pattern in a first direction parallel with the substrate and a landing sidewall portion upwardly extending from an end of the flat portion. A width of a portion of the landing sidewall portion in a second direction parallel with the substrate and perpendicular to the first direction is less than a width of the flat portion in the second direction. The related methods are also provided.

    摘要翻译： 提供半导体器件。 半导体器件包括垂直堆叠在基板上以彼此间隔开的导电图案，以及电连接到相应导电图案的焊盘图案。 每个焊盘图案包括从平行于基板的第一方向从导电图案的端部延伸的平坦部分和从平坦部分的端部向上延伸的着陆侧壁部分。 着陆侧壁部的与基板平行且垂直于第一方向的第二方向的一部分的宽度小于第二方向上的平坦部的宽度。 还提供了相关方法。

    Nonvolatile memory devices having a three dimensional structure
    7.
    发明授权
    Nonvolatile memory devices having a three dimensional structure 有权
    具有三维结构的非易失性存储器件

    公开(公告)号：US08203211B2

    公开(公告)日：2012-06-19

    申请号：US12798525

    申请日：2010-04-06

    申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    IPC分类号： H01L27/115 ,  H01L23/522

    CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

    摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

    摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸，以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

    Nonvolatile memory devices
    9.
    发明申请
    Nonvolatile memory devices 有权
    非易失性存储器件

    公开(公告)号：US20100258947A1

    公开(公告)日：2010-10-14

    申请号：US12798525

    申请日：2010-04-06

    申请人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    发明人： Jaehun Jeong ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho ,  Kyoung-Hoon Kim

    IPC分类号： H01L27/115 ,  H01L23/522

    CPC分类号： H01L27/11578 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11582

    摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays.

    摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件可以包括具有三维布置在半导体衬底上的线形状的多个导电图案的单元阵列，单元阵列彼此分离; 从半导体衬底延伸到导电图案的横截面的半导体图案; 在所述半导体图案的下部设置在所述半导体衬底中的在所述导电图案延伸的方向上的公共源极区; 设置在所述半导体衬底中的第一杂质区域，使得所述第一杂质区域沿与所述导电图案交叉的方向延伸以电连接所述公共源极区域; 以及在分离的电池阵列之间暴露第一杂质区域的一部分的第一接触孔。

    Method of forming a three-dimensional semiconductor memory device comprising sub-cells, terraced structures and strapping regions
    10.
    发明授权
    Method of forming a three-dimensional semiconductor memory device comprising sub-cells, terraced structures and strapping regions 有权
    形成三维半导体存储器件的方法，其包括子单元，梯形结构和捆扎区域

    公开(公告)号：US08603906B2

    公开(公告)日：2013-12-10

    申请号：US13779334

    申请日：2013-02-27

    申请人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

    发明人： Sunil Shim ,  Sunghoi Hur ,  Hansoo Kim ,  Jaehoon Jang ,  Hoosung Cho

    IPC分类号： H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/02365 ,  H01L21/02697 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582

    摘要： Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level.

    摘要翻译： 提供一种三维半导体存储器件。 三维半导体存储器件包括具有包括一对子单元区域的单元阵列区域和插入该一对子单元区域之间的带状区域的基板。 多个子栅极依次层叠在每个子单元区域中的衬底上，并且互连电连接到延伸到捆扎区域中的堆叠子栅极的延伸部分。 每个互连电连接到分别设置在一对子单元区域中并且位于同一电平的子栅极的延伸部分。