公开(公告)号：US06447604B1

公开(公告)日：2002-09-10

申请号：US09605195

申请日：2000-06-28

申请人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo ,  David M. Keogh ,  Xueping Xu ,  Barbara E. Landini

发明人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo ,  David M. Keogh ,  Xueping Xu ,  Barbara E. Landini

IPC分类号： C30B2514

CPC分类号： C30B25/02 ,  C30B23/002 ,  C30B23/02 ,  C30B25/00 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/02658 ,  H01L33/32 ,  H01S5/1228 ,  H01S5/1231 ,  H01S5/2095 ,  H01S5/32341

摘要： A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.

摘要翻译： III-V族氮化物同质外延微电子器件结构，其包括III-V族氮化物材料衬底上的III-V族同质外延层，例如独立性。 描述了各种处理技术，包括通过使用III族源材料和氮源材料通过VPE工艺沉积III-V族氮化物同质外延层，在相应的III-V族氮化物材料基板上形成III-V族氮化物同质外延层的方法 在包括约1至约105范围内的V / III比的工艺条件下，氮源材料分压在约1至约103托的范围内，生长温度在约500至约1250摄氏度的范围内 ，并且生长速率在约0.1至约500微米/小时的范围内。 III-V族氮化物同质外延微电子器件结构有用地用于诸如UV LED，高电子迁移率晶体管等的器件应用中。

公开(公告)号：US08390101B2

公开(公告)日：2013-03-05

申请号：US13428039

申请日：2012-03-23

申请人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo

发明人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo

IPC分类号： H01L29/20

CPC分类号： H01L29/2003 ,  C30B25/02 ,  C30B29/40 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02664 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

摘要： The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration ( 2 KV).

摘要翻译： 本发明涉及包括肖特基二极管，PN二极管和PIN二极管的各种开关器件结构，其特征在于低缺陷密度，低裂纹密度，低凹坑密度和足够厚度（>2.5μm）低掺杂剂浓度的GaN层（ 在导电GaN层上生长的<1E16cm-3）。 这些器件在异质外延衬底（<2KV）上实现了更高的击穿电压，并且在同质外延衬底（> 2KV）上实现了极高的击穿电压。

公开(公告)号：US20120181547A1

公开(公告)日：2012-07-19

申请号：US13428039

申请日：2012-03-23

申请人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo

发明人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo

IPC分类号： H01L29/20

CPC分类号： H01L29/2003 ,  C30B25/02 ,  C30B29/40 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02664 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

摘要： The present invention relates to various switching device structures including Schottky diode, P-N diode, and P-I-N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration ( 2 KV).

摘要翻译： 本发明涉及包括肖特基二极管，PN二极管和PIN二极管的各种开关器件结构，其特征在于低缺陷密度，低裂纹密度，低凹坑密度和足够厚度（>2.5μm）低掺杂剂浓度的GaN层（ 在导电GaN层上生长的<1E16cm-3）。 这些器件在异质外延衬底（<2KV）上实现了更高的击穿电压，并且在同质外延衬底（> 2KV）上实现了极高的击穿电压。

公开(公告)号：US08043731B2

公开(公告)日：2011-10-25

申请号：US12713514

申请日：2010-02-26

申请人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

发明人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC分类号： B32B18/00 ,  B32B11/08

CPC分类号： C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

摘要： A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3 E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

摘要翻译： III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中表面具有通过50×50μm2 AFM扫描测量的RMS粗糙度小于1nm，位错密度小于3E6cm-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 上表面和下表面都可以被切断。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。

公开(公告)号：US20100301351A1

公开(公告)日：2010-12-02

申请号：US12852223

申请日：2010-08-06

申请人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo

发明人： Jeffrey S. Flynn ,  George R. Brandes ,  Robert P. Vaudo

IPC分类号： H01L29/20 ,  H01L29/24

CPC分类号： H01L29/2003 ,  C30B25/02 ,  C30B29/40 ,  C30B29/406 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02664 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

摘要： The present invention relates to various switching device structures including Schottky diode, P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers of low dopant concentration ( 2 KV).

摘要翻译： 本发明涉及包括肖特基二极管，P-N二极管和P-I-N二极管的各种开关器件结构，其特征在于低缺陷密度，低裂纹密度，低凹坑密度和足够的厚度（>2.5μm）GaN 在导电GaN层上生长的低掺杂浓度（<1E16cm-3）层。 这些器件在异质外延衬底（<2KV）上实现了更高的击穿电压，并且在同质外延衬底（> 2KV）上实现了极高的击穿电压。

公开(公告)号：US20100148320A1

公开(公告)日：2010-06-17

申请号：US12713514

申请日：2010-02-26

申请人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

发明人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC分类号： H01L29/04 ,  H01L21/306 ,  B26D3/00

CPC分类号： C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

摘要： A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. Both upper and lower surfaces may be offcut. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

摘要翻译： III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中该表面具有通过50×50μm2 AFM扫描测量的RMS粗糙度小于1nm，位错密度小于3E6cm-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 上表面和下表面都可以被切断。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。

公开(公告)号：US07118813B2

公开(公告)日：2006-10-10

申请号：US10714307

申请日：2003-11-14

申请人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

发明人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC分类号： C30B23/02 ,  C30B29/38 ,  C30B29/40 ,  B32B9/00

CPC分类号： C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

摘要： A III–V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III–V nitride-based microelectronic and opto-electronic devices.

公开(公告)号：US07915152B2

公开(公告)日：2011-03-29

申请号：US12698144

申请日：2010-02-02

申请人： Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes ,  Joan M. Redwing ,  Michael A. Tischler

发明人： Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes ,  Joan M. Redwing ,  Michael A. Tischler

IPC分类号： B01D9/00 ,  A61L2/00 ,  C30B23/00 ,  C30B29/38 ,  H01L21/00 ,  H01L21/44 ,  H01L21/31 ,  H01L33/00 ,  H01L29/04 ,  B32B19/00

CPC分类号： H01L33/32 ,  C30B23/00 ,  C30B25/00 ,  C30B25/02 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/0262

摘要： A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

摘要翻译： 通过在天然氮化物种子上的III-V族氮化物块（锭）的高速气相生长形成的毛坯，可以从其中衍生出用于制造微电子器件结构的晶片。 该微孔具有微电子器件的质量，例如横向尺寸大于1厘米，长度大于1毫米，顶表面缺陷密度小于107缺陷cm-2。 III-V族氮化物坯料可以通过在相对的天然III-V族氮化物晶种上以20微米/小时的生长速率通过气相外延生长III-V族氮化物材料来形成。 核变换掺杂可以应用于（Al，Ga，In）N制品，其包括晶粒，晶片或外延层。

公开(公告)号：US20100289122A1

公开(公告)日：2010-11-18

申请号：US12698144

申请日：2010-02-02

申请人： Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes ,  Joan M. Redwing ,  Michael A. Tischler

发明人： Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes ,  Joan M. Redwing ,  Michael A. Tischler

IPC分类号： H01L29/20 ,  H01L21/20 ,  H01L21/22

CPC分类号： H01L33/32 ,  C30B23/00 ,  C30B25/00 ,  C30B25/02 ,  C30B25/183 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02581 ,  H01L21/0262

摘要： A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 107 defects cm−2. The Group III-V nitride boule may be formed by growing a Group III-V nitride material on a corresponding native Group III-V nitride seed crystal by vapor phase epitaxy at a growth rate above 20 micrometers per hour. Nuclear transmutation doping may be applied to an (Al,Ga,In)N article comprises a boule, wafer, or epitaxial layer.

摘要翻译： 通过在天然氮化物种子上的III-V族氮化物块（锭）的高速气相生长形成的毛坯，可以从其中衍生出用于制造微电子器件结构的晶片。 该微孔具有微电子器件的质量，例如横向尺寸大于1厘米，长度大于1毫米，顶表面缺陷密度小于107缺陷cm-2。 III-V族氮化物坯料可以通过在相对的天然III-V族氮化物晶种上以20微米/小时的生长速率通过气相外延生长III-V族氮化物材料来形成。 核变换掺杂可以应用于（Al，Ga，In）N制品，其包括晶粒，晶片或外延层。

公开(公告)号：US20080199649A1

公开(公告)日：2008-08-21

申请号：US12102275

申请日：2008-04-14

申请人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

发明人： Xueping Xu ,  Robert P. Vaudo ,  Jeffrey S. Flynn ,  George R. Brandes

IPC分类号： B32B3/02 ,  C01B21/00 ,  C01B21/06 ,  C01B21/072 ,  H01L31/00 ,  B32B9/00

CPC分类号： C30B29/403 ,  C30B25/18 ,  C30B29/406 ,  H01L29/045 ,  H01L29/2003 ,  Y10T83/0524 ,  Y10T428/31

摘要： A III-V nitride, e.g., GaN, substrate including a (0001) surface offcut from the direction predominantly toward a direction selected from the group consisting of and directions, at an offcut angle in a range that is from about 0.2 to about 10 degrees, wherein the surface has a RMS roughness measured by 50×50 μm2 AFM scan that is less than 1 nm, and a dislocation density that is less than 3E6 cm−2. The substrate may be formed by offcut slicing of a corresponding boule or wafer blank, by offcut lapping or growth of the substrate body on a corresponding vicinal heteroepitaxial substrate, e.g., of offcut sapphire. The substrate is usefully employed for homoepitaxial deposition in the fabrication of III-V nitride-based microelectronic and opto-electronic devices.

摘要翻译： III-V族氮化物，例如GaN，衬底，其包括从<0001>方向切除的（0001）表面主要朝向选自<10-10>和<11-20>方向的方向切割 在约0.2至约10度的范围内的角度，其中表面具有通过50×50μm2μmAFM扫描测量的RMS粗糙度小于1nm，位错密度小于 3E6厘米-2。 可以通过在对应的邻位异质外延基底（例如切断蓝宝石）上的基底主体的切削研磨或生长来对对应的原子块或晶片坯料进行切割切片来形成基底。 在制造III-V族氮化物微电子和光电子器件时，该衬底有效地用于同质外延沉积。