公开(公告)号：US6137141A

公开(公告)日：2000-10-24

申请号：US69867

申请日：1998-04-30

申请人： Jeong Hwan Son ,  Ki Jae Huh

发明人： Jeong Hwan Son ,  Ki Jae Huh

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/7833 ,  H01L29/66545

摘要： A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process. The present invention is directed most generally to a semiconductor device which includes: a semiconductor substrate of a first conductivity type; a gate insulator on the substrate, the gate insulator sharing an interface with the substrate; a gate electrode on the gate insulator, the gate electrode having a first side, a second side, and a middle region between the first and second sides; a source doped region of a second conductivity type within the substrate to the first side of the gate electrode and a drain doped region of the second conductivity type within the substrate to the second side of the gate electrode, the source and drain doped regions self-aligned to the gate electrode; and a channel doped region of the first conductivity type within the substrate below the gate electrode, the channel doped region having a peak dopant concentration profile such that the peak dopant concentration under the middle region of the gate electrode occurs further below the gate insulator-substrate interface than does either the peak dopant concentration under the first side of the gate electrode or the peak dopant concentration under the second side of the gate electrode.

摘要翻译： 通过离子注入通过非均匀截面的多晶硅栅电极获得沟道区中的不均匀掺杂剂浓度的金属氧化物半导体（MOS）器件，其本身是通过使用半加工的LOCOS工艺氧化多晶硅而获得的 。 本发明最为普遍地涉及一种半导体器件，它包括：第一导电类型的半导体衬底; 基板上的栅极绝缘体，栅极绝缘体与衬底共用界面; 所述栅电极在所述栅绝缘体上具有第一侧和第二侧之间的第一侧，第二侧和中间区; 在栅极电极的第一侧的衬底内的第二导电类型的源极掺杂区域和衬底内的第二导电类型的漏极掺杂区域到栅电极的第二侧， 与栅电极对准; 以及在栅电极下方的衬底内的第一导电类型的沟道掺杂区域，沟道掺杂区域具有峰值掺杂浓度分布，使得栅极电极的中间区域附近的峰值掺杂剂浓度进一步低于栅绝缘体衬底 界面比在栅电极的第一侧下的峰值掺杂浓度或栅电极的第二侧下的峰值掺杂剂浓度。

公开(公告)号：US06383876B1

公开(公告)日：2002-05-07

申请号：US09627298

申请日：2000-07-27

申请人： Jeong Hwan Son ,  Ki Jae Huh

发明人： Jeong Hwan Son ,  Ki Jae Huh

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/7833

摘要： A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process. The present invention is directed most generally to a semiconductor device which includes: a semiconductor substrate of a first conductivity type; a gate insulator on the substrate, the gate insulator sharing an interface with the substrate; a gate electrode on the gate insulator, the gate electrode having a first side, a second side, and a middle region between the first and second sides; a source doped region of a second conductivity type within the substrate to the first side of the gate electrode and a drain doped region of the second conductivity type within the substrate to the second side of the gate electrode, the source and drain doped regions self-aligned to the gate electrode; and a channel doped region of the first conductivity type within the substrate below the gate electrode, the channel doped region having a peak dopant concentration profile such that the peak dopant concentration under the middle region of the gate electrode occurs further below the gate insulator-substrate interface than does either the peak dopant concentration under the first side of the gate electrode or the peak dopant concentration under the second side of the gate electrode.

摘要翻译： 通过离子注入通过非均匀截面的多晶硅栅电极获得沟道区中的不均匀掺杂剂浓度的金属氧化物半导体（MOS）器件，其本身是通过使用半加工的LOCOS工艺氧化多晶硅而获得的 。 本发明最为普遍地涉及一种半导体器件，它包括：第一导电类型的半导体衬底; 基板上的栅极绝缘体，栅极绝缘体与衬底共用界面; 所述栅电极在所述栅绝缘体上具有第一侧和第二侧之间的第一侧，第二侧和中间区; 在栅极电极的第一侧的衬底内的第二导电类型的源极掺杂区域和衬底内的第二导电类型的漏极掺杂区域到栅电极的第二侧， 与栅电极对准; 以及在栅电极下方的衬底内的第一导电类型的沟道掺杂区域，沟道掺杂区域具有峰值掺杂浓度分布，使得栅极电极的中间区域附近的峰值掺杂剂浓度进一步低于栅绝缘体衬底 界面比在栅电极的第一侧下的峰值掺杂浓度或栅电极的第二侧下的峰值掺杂剂浓度。

公开(公告)号：US5877068A

公开(公告)日：1999-03-02

申请号：US784062

申请日：1997-01-17

申请人： Ki Jae Huh ,  Jeong Hwan Son

发明人： Ki Jae Huh ,  Jeong Hwan Son

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76202

摘要： A method for forming an isolating layer in a semiconductor device includes the steps of forming a first material layer on an active layer having a major axis and a minor axis, forming a second material layer in a form of sidewall at sides of the first material layer in a direction of the major axis, and conducting field oxidation using the first and second material layers as masks to form the isolating layer.

摘要翻译： 在半导体器件中形成绝缘层的方法包括以下步骤：在具有长轴和短轴的有源层上形成第一材料层，在第一材料层的侧面形成侧壁形式的第二材料层 在长轴的方向上，并且使用第一和第二材料层作为掩模进行场氧化以形成隔离层。

公开(公告)号：US06180473B2

公开(公告)日：2001-01-30

申请号：US09468123

申请日：1999-12-21

申请人： Sung Kwon Hong ,  Jeong Hwan Son ,  Jae Gyung Ahn ,  Jeong Mo Hwang

发明人： Sung Kwon Hong ,  Jeong Hwan Son ,  Jae Gyung Ahn ,  Jeong Mo Hwang

IPC分类号： H01L21336

CPC分类号： H01L21/823418 ,  H01L21/26506 ,  H01L21/82345 ,  H01L21/823462

摘要： A method for manufacturing a semiconductor device improves hot carrier characteristic in a device having a thick gate insulating film without being affected by short channel effect, thereby improving reliability of the device. The method for manufacturing a semiconductor device includes the steps of forming gate electrodes having gate insulating films of different thicknesses on a semiconductor substrate, implanting a low-concentration impurity ion into the semiconductor substrate at both sides of the gate electrodes, implanting a nitrogen ion into a portion, where the low-concentration impurity ion is implanted, in the gate insulating film relatively thicker than the other gate insulating film, forming sidewall spacers at both sides of the gate electrodes, and implanting a high-concentration source/drain impurity ion into the semiconductor substrate.

摘要翻译： 半导体器件的制造方法，在不影响短沟道效应的情况下，能够提高具有厚栅绝缘膜的器件中的热载流子特性，提高器件的可靠性。 半导体器件的制造方法包括以下步骤：在半导体衬底上形成具有不同厚度的栅极绝缘膜的栅电极，将低浓度杂质离子注入到栅电极两侧的半导体衬底中，将氮离子注入 在栅绝缘膜中相对于另一个栅极绝缘膜相对厚的部分，其中注入低浓度杂质离子，在栅电极的两侧形成侧壁间隔物，并将高浓度源/漏杂质离子注入 半导体衬底。

公开(公告)号：US6110769A

公开(公告)日：2000-08-29

申请号：US197580

申请日：1998-11-23

申请人： Jeong Hwan Son

发明人： Jeong Hwan Son

IPC分类号： H01L27/12 ,  H01L21/02 ,  H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L21/76

CPC分类号： H01L29/78612 ,  H01L21/84 ,  Y10S438/977

摘要： An SOI device and a method for fabricating the same in which floating body effect is reduced and the performance is thus improved are disclosed, the SOI device including a semiconductor substrate; a first buried insualting film formed on the semiconductor substrate; a first conductivity type silicon layer formed on the first buried insulating film; an active region and a first conductivity type semiconductor layer formed to be isolated on predetermined areas of the first conductivity type silicon layer; second buried insulating films formed to be isolated from one another in the first conductivity type silicon layer to connect the first conductivity type semiconductor layer with the active region through the first conductivity type silicon layer; a gate electrode formed on the active region; impurity region formed in the semiconductor substrate at both sides of the gate electrode; and contact pads formed on the first conductivity type silicon layer.

摘要翻译： 公开了一种SOI器件及其制造方法，其中浮体效应降低并且性能得到改善，SOI器件包括半导体衬底; 形成在半导体衬底上的第一掩埋绝缘膜; 形成在第一掩埋绝缘膜上的第一导电型硅层; 形成为在第一导电型硅层的预定区域上隔离的有源区和第一导电类型半导体层; 在第一导电型硅层中形成为彼此隔离的第二掩埋绝缘膜，以通过第一导电型硅层将第一导电类型半导体层与有源区连接; 形成在有源区上的栅电极; 杂质区域形成在栅电极两侧的半导体衬底中; 以及形成在第一导电型硅层上的接触焊盘。

公开(公告)号：US6023088A

公开(公告)日：2000-02-08

申请号：US85016

申请日：1998-05-28

申请人： Jeong Hwan Son

发明人： Jeong Hwan Son

IPC分类号： H01L21/22 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/786 ,  B32B5/16

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L29/78612 ,  H01L29/78654 ,  H01L21/26506 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/66545

摘要： The semiconductor device includes and the method for fabricating the same forms a damaged region under a gate electrode to improve device performance and simplify the process. The semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in first predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed over a second predetermined area of the substrate; sidewall spacers formed on both sides of the gate electrode; source and drain regions at both sides of the gate electrode; and the damaged region at boundary of the buried insulating layer under the gate electrode.

摘要翻译： 半导体器件包括并且其制造方法在栅电极下形成损坏区域以提高器件性能并简化工艺。 半导体器件包括其中形成掩埋绝缘层的衬底; 掩埋在所述衬底的第一预定区域中以与所述掩埋绝缘层接触的器件隔离层; 形成在所述基板的第二预定区域上的栅电极; 侧壁间隔物形成在栅电极的两侧; 源极和漏极区域在栅电极的两侧; 以及在栅电极下的掩埋绝缘层的边界处的损坏区域。

公开(公告)号：US06218248B1

公开(公告)日：2001-04-17

申请号：US09285258

申请日：1999-04-02

申请人： Jeong Mo Hwang ,  Jeong Hwan Son

发明人： Jeong Mo Hwang ,  Jeong Hwan Son

IPC分类号： H01L21336

CPC分类号： H01L21/84 ,  H01L27/0218 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

摘要翻译： 公开了一种半导体器件及其制造方法，其中通过向SOI MOSFET中的主体施加偏压来降低浮体效应。 半导体器件包括形成在半导体衬底中的第一和第二杂质离子注入层，该半导体衬底具有掩埋氧化膜和其上的表面硅层，分别形成在第一和第二杂质离子注入层上的导电类型的第一和第二晶体管 具有源极/漏极区域和栅极，形成在第一和第二晶体管之间的沟槽，连接到相应晶体管的源极/漏极区域中的任何一个的单晶硅层，以及在第一和第二晶体管的侧面处的第一和第二杂质离子注入层 沟槽和载体排出电极，其连接到相应晶体管的一侧处的第一和第二杂质离子注入层，用于排出由各个晶体管中的电离冲击产生的载流子。

公开(公告)号：US6103562A

公开(公告)日：2000-08-15

申请号：US225314

申请日：1999-01-05

申请人： Jeong Hwan Son ,  Young Gwan Kim

发明人： Jeong Hwan Son ,  Young Gwan Kim

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L21/823842 ,  Y10S438/919

摘要： Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

摘要翻译： 公开了半导体器件及其制造方法，即使沟道宽度减小，也可以保持阈值电压恒定，该器件包括衬底中的第一和第二导电型阱，第一栅极绝缘膜和第二栅极绝缘膜 在第一栅极绝缘膜上的第一栅电极和第二导电类型阱中的第一栅电极，第一栅电极掺杂有第二导电类型，除了第一栅电极的边缘在沟道宽度方向上掺杂有 第一导电类型，第二栅极绝缘膜上的第二栅电极，在掺杂有第二导电类型的沟道宽度方向上的第二栅电极的边缘以外掺杂第一导电类型的第二栅电极，以及隔离区 形成在第一和第二导电类型的阱，第一和第二栅极绝缘膜以及第一和第二栅电极之间。

公开(公告)号：US06537927B1

公开(公告)日：2003-03-25

申请号：US09324657

申请日：1999-06-03

申请人： Jeong Hwan Son

发明人： Jeong Hwan Son

IPC分类号： H01L2100

CPC分类号： H01L21/67115

摘要： A method and apparatus for heat-treating a semiconductor substrate to heat different areas of the substrate at different temperatures. The method includes using an apparatus having a chamber of a refractory material; a support plate located at a lower side in the chamber for supporting the semiconductor substrate; a heating device disposed at an upper side in the chamber; and, a heat resistance mask provided between the support plate and fabricated to have different heat transmission rates therein.

摘要翻译： 一种用于热处理半导体衬底以在不同温度下加热衬底的不同区域的方法和装置。 该方法包括使用具有耐火材料室的设备; 支撑板，位于所述腔室中的下侧，用于支撑所述半导体衬底; 设置在所述室中的上侧的加热装置; 以及设置在支撑板之间并被制造成具有不同的传热速率的耐热掩模。

公开(公告)号：US6069056A

公开(公告)日：2000-05-30

申请号：US998828

申请日：1997-12-29

申请人： Jeong Hwan Son ,  Jong Kwan Kim

发明人： Jeong Hwan Son ,  Jong Kwan Kim

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/31056

摘要： A method of forming an isolation region of a semiconductor device, includes the steps of forming a first insulating film on a substrate; defining a plurality of isolation regions on the first insulating film; removing portions of the first insulating film in the isolation regions to expose portions of the substrate; selectively removing the exposed portions of the substrate to form at least one trench; forming a second insulating film in the at least one trench and on portions of the first insulating film; and removing the first insulating film so as to remove the second insulating film formed thereon.

摘要翻译： 一种形成半导体器件的隔离区域的方法，包括在衬底上形成第一绝缘膜的步骤; 在所述第一绝缘膜上限定多个隔离区; 去除所述隔离区域中的所述第一绝缘膜的部分以暴露所述衬底的部分; 选择性地去除衬底的暴露部分以形成至少一个沟槽; 在所述至少一个沟槽中和所述第一绝缘膜的一部分上形成第二绝缘膜; 以及去除所述第一绝缘膜以除去其上形成的所述第二绝缘膜。