公开(公告)号：US06362060B1

公开(公告)日：2002-03-26

申请号：US09879200

申请日：2001-06-13

申请人： Jae-Gyung Ahn ,  Jeong-Hwan Son

发明人： Jae-Gyung Ahn ,  Jeong-Hwan Son

IPC分类号： H01L21336

摘要： A trench or a recess is formed in a predetermined part of a semiconductor substrate. Then, on the side of the trench or recess, a gate with a sidewall is formed by respective etching-back processes. Using the gate as a mask, a low concentration region for the LDD structure is formed. Using the gate and sidewall as a mask, a source region and a drain region are formed. Thus, the channel region makes a right angle with the trench or recess, and the channel region is bent. Further, the channel region is made to be formed so as to be longer than the width of the gate. Since the low concentration region for the LDD structure is formed only in the drain region, the source resistance can be decreased, and a gate with a narrow width can be easily formed. Further, even if the channel length is short, the occurrence of the DIBL phenomenon can be suppressed.

公开(公告)号：US06358805B2

公开(公告)日：2002-03-19

申请号：US09114934

申请日：1998-07-14

申请人： Jeong-Hwan Son ,  Hyeong-Mo Yang

发明人： Jeong-Hwan Son ,  Hyeong-Mo Yang

IPC分类号： H01L23336

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/78612 ,  H01L29/78618

摘要： In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed on the buried insulating layer and separated from one another, a field oxide layer is formed among the depletion regions of the buried insulating layer, a gate oxide layer is formed on the depletion regions, a gate is formed on the gate oxide layer, impurity regions that are heavily doped with impurities of a second conductivity type is formed in the depletion regions on both sides of the gate to define a source and drain, and a counter doping layer that is lightly doped with impurities of the second conductivity type is formed under the channel defined by a portion of the depletion regions positioned between the impurity regions. The counter doping layer is formed at a predetermined or fixed distance from the upper surface of the depletion region defining the channel, overlapping the lower portion of the depletion region to achieve uniform thickness in at least a portion of the depletion region.

摘要翻译： 在半导体装置及其制造方法中，在半导体基板上形成埋入绝缘层，在掩埋绝缘层上形成多个第一导电类型的耗尽区，并将其分离，形成场氧化物层 掩埋绝缘层的耗尽区，在耗尽区上形成栅极氧化层，在栅极氧化层上形成栅极，在耗尽区形成重掺杂第二导电型杂质的杂质区 栅极的两侧限定源极和漏极，并且在由位于杂质区域之间的耗尽区的一部分限定的沟道下方形成在轻掺杂有第二导电类型的杂质的反掺杂层。 反向掺杂层形成在与限定沟道的耗尽区的上表面预定或固定的距离处，与耗尽区的下部重叠，以在耗尽区的至少一部分中实现均匀的厚度。

公开(公告)号：US06225682B1

公开(公告)日：2001-05-01

申请号：US09046631

申请日：1998-03-24

申请人： Jeong-Hwan Son

发明人： Jeong-Hwan Son

IPC分类号： H01L2358

CPC分类号： H01L21/76202

摘要： A fabrication method for a semiconductor memory device having an isolation structure which includes the steps of forming a pad oxide film on a semiconductor substrate, forming a first nitride film on the pad oxide film, patterning the first nitride film and the pad oxide film, forming an oxynitride film on a portion of the substrate externally exposed by the patterning step, forming side walls of a second nitride film on sides of the first nitride film, removing a portion of the oxynitride film using the side walls as a mask, forming a field oxide film on an exposed portion of the substrate, and removing the remaining pad oxide film, first nitride film, second nitride film, and oxynitride film. The first nitrate film and the pad oxide film may be patterned such that the pad oxide film is undercut to expose more of the substrate and to allow formation of the oxynitride film under the first nitride film. As such, the first nitride film can be used as a mask, rendering unnecessary the formation of side walls. The method simultaneously employs an oxide film and an oxynitride film to decrease a bird's beak generation while minimizing stress resulting from the oxynitride film.

摘要翻译： 一种具有隔离结构的半导体存储器件的制造方法，包括以下步骤：在半导体衬底上形成衬垫氧化膜，在衬垫氧化膜上形成第一氮化物膜，对第一氮化物膜和衬垫氧化膜进行图案化，形成 通过图案化步骤在外部暴露的衬底的一部分上的氧氮化物膜，在第一氮化物膜的侧面上形成第二氮化物膜的侧壁，使用侧壁作为掩模去除一部分氮氧化物膜，形成场 氧化膜，去除剩余的衬垫氧化膜，第一氮化物膜，第二氮化物膜和氮氧化物膜。 可以对第一硝酸盐膜和衬垫氧化物膜进行图案化，使得衬垫氧化物膜被底切以暴露更多的衬底并且允许在第一氮化物膜下方形成氧氮化物膜。 因此，可以将第一氮化物膜用作掩模，从而不必形成侧壁。 该方法同时使用氧化膜和氧氮化物膜来减少鸟的喙产生，同时使由氮氧化物膜产生的应力最小化。

公开(公告)号：US06180473B2

公开(公告)日：2001-01-30

申请号：US09468123

申请日：1999-12-21

申请人： Sung Kwon Hong ,  Jeong Hwan Son ,  Jae Gyung Ahn ,  Jeong Mo Hwang

发明人： Sung Kwon Hong ,  Jeong Hwan Son ,  Jae Gyung Ahn ,  Jeong Mo Hwang

IPC分类号： H01L21336

CPC分类号： H01L21/823418 ,  H01L21/26506 ,  H01L21/82345 ,  H01L21/823462

摘要： A method for manufacturing a semiconductor device improves hot carrier characteristic in a device having a thick gate insulating film without being affected by short channel effect, thereby improving reliability of the device. The method for manufacturing a semiconductor device includes the steps of forming gate electrodes having gate insulating films of different thicknesses on a semiconductor substrate, implanting a low-concentration impurity ion into the semiconductor substrate at both sides of the gate electrodes, implanting a nitrogen ion into a portion, where the low-concentration impurity ion is implanted, in the gate insulating film relatively thicker than the other gate insulating film, forming sidewall spacers at both sides of the gate electrodes, and implanting a high-concentration source/drain impurity ion into the semiconductor substrate.

摘要翻译： 半导体器件的制造方法，在不影响短沟道效应的情况下，能够提高具有厚栅绝缘膜的器件中的热载流子特性，提高器件的可靠性。 半导体器件的制造方法包括以下步骤：在半导体衬底上形成具有不同厚度的栅极绝缘膜的栅电极，将低浓度杂质离子注入到栅电极两侧的半导体衬底中，将氮离子注入 在栅绝缘膜中相对于另一个栅极绝缘膜相对厚的部分，其中注入低浓度杂质离子，在栅电极的两侧形成侧壁间隔物，并将高浓度源/漏杂质离子注入 半导体衬底。

公开(公告)号：US6137141A

公开(公告)日：2000-10-24

申请号：US69867

申请日：1998-04-30

申请人： Jeong Hwan Son ,  Ki Jae Huh

发明人： Jeong Hwan Son ,  Ki Jae Huh

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/2652 ,  H01L21/266 ,  H01L21/28114 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66537 ,  H01L29/7833 ,  H01L29/66545

摘要： A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process. The present invention is directed most generally to a semiconductor device which includes: a semiconductor substrate of a first conductivity type; a gate insulator on the substrate, the gate insulator sharing an interface with the substrate; a gate electrode on the gate insulator, the gate electrode having a first side, a second side, and a middle region between the first and second sides; a source doped region of a second conductivity type within the substrate to the first side of the gate electrode and a drain doped region of the second conductivity type within the substrate to the second side of the gate electrode, the source and drain doped regions self-aligned to the gate electrode; and a channel doped region of the first conductivity type within the substrate below the gate electrode, the channel doped region having a peak dopant concentration profile such that the peak dopant concentration under the middle region of the gate electrode occurs further below the gate insulator-substrate interface than does either the peak dopant concentration under the first side of the gate electrode or the peak dopant concentration under the second side of the gate electrode.

摘要翻译： 通过离子注入通过非均匀截面的多晶硅栅电极获得沟道区中的不均匀掺杂剂浓度的金属氧化物半导体（MOS）器件，其本身是通过使用半加工的LOCOS工艺氧化多晶硅而获得的 。 本发明最为普遍地涉及一种半导体器件，它包括：第一导电类型的半导体衬底; 基板上的栅极绝缘体，栅极绝缘体与衬底共用界面; 所述栅电极在所述栅绝缘体上具有第一侧和第二侧之间的第一侧，第二侧和中间区; 在栅极电极的第一侧的衬底内的第二导电类型的源极掺杂区域和衬底内的第二导电类型的漏极掺杂区域到栅电极的第二侧， 与栅电极对准; 以及在栅电极下方的衬底内的第一导电类型的沟道掺杂区域，沟道掺杂区域具有峰值掺杂浓度分布，使得栅极电极的中间区域附近的峰值掺杂剂浓度进一步低于栅绝缘体衬底 界面比在栅电极的第一侧下的峰值掺杂浓度或栅电极的第二侧下的峰值掺杂剂浓度。

公开(公告)号：US06537927B1

公开(公告)日：2003-03-25

申请号：US09324657

申请日：1999-06-03

申请人： Jeong Hwan Son

发明人： Jeong Hwan Son

IPC分类号： H01L2100

CPC分类号： H01L21/67115

摘要： A method and apparatus for heat-treating a semiconductor substrate to heat different areas of the substrate at different temperatures. The method includes using an apparatus having a chamber of a refractory material; a support plate located at a lower side in the chamber for supporting the semiconductor substrate; a heating device disposed at an upper side in the chamber; and, a heat resistance mask provided between the support plate and fabricated to have different heat transmission rates therein.

摘要翻译： 一种用于热处理半导体衬底以在不同温度下加热衬底的不同区域的方法和装置。 该方法包括使用具有耐火材料室的设备; 支撑板，位于所述腔室中的下侧，用于支撑所述半导体衬底; 设置在所述室中的上侧的加热装置; 以及设置在支撑板之间并被制造成具有不同的传热速率的耐热掩模。

公开(公告)号：US6069056A

公开(公告)日：2000-05-30

申请号：US998828

申请日：1997-12-29

申请人： Jeong Hwan Son ,  Jong Kwan Kim

发明人： Jeong Hwan Son ,  Jong Kwan Kim

IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/31056

摘要： A method of forming an isolation region of a semiconductor device, includes the steps of forming a first insulating film on a substrate; defining a plurality of isolation regions on the first insulating film; removing portions of the first insulating film in the isolation regions to expose portions of the substrate; selectively removing the exposed portions of the substrate to form at least one trench; forming a second insulating film in the at least one trench and on portions of the first insulating film; and removing the first insulating film so as to remove the second insulating film formed thereon.

摘要翻译： 一种形成半导体器件的隔离区域的方法，包括在衬底上形成第一绝缘膜的步骤; 在所述第一绝缘膜上限定多个隔离区; 去除所述隔离区域中的所述第一绝缘膜的部分以暴露所述衬底的部分; 选择性地去除衬底的暴露部分以形成至少一个沟槽; 在所述至少一个沟槽中和所述第一绝缘膜的一部分上形成第二绝缘膜; 以及去除所述第一绝缘膜以除去其上形成的所述第二绝缘膜。

公开(公告)号：US6063681A

公开(公告)日：2000-05-16

申请号：US118823

申请日：1998-07-20

申请人： Jeong Hwan Son

发明人： Jeong Hwan Son

IPC分类号： H01L21/285 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/6653

摘要： Semiconductor device and method for fabricating the same, is disclosed, in which LDD regions and source/drain regions are provided with a silicide for reducing resistances to prevent short channel, the device including a gate insulating film and a gate electrode formed stacked on a prescribed region of a semiconductor substrate, sidewall spacers formed at both sides of the gate insulating film and the gate electrode, first impurity regions formed in surfaces of the semiconductor substrate under the sidewall spacers, second impurity regions formed in the semiconductor substrate on both sides of the sidewall spacers and the first impurity regions, first silicide films at surfaces of the first impurity regions, and second silicide films at surfaces of the gate electrode and the second impurity regions.

摘要翻译： 半导体装置及其制造方法公开了其中LDD区域和源极/漏极区域设置有用于降低电阻以防止短沟道的硅化物，该器件包括堆叠在规定的栅极绝缘膜和栅电极 半导体衬底的两个侧面上形成的侧壁隔离物和形成在该半导体衬底的侧壁间隔的表面的第一杂质区，形成在该半导体衬底的两侧的第二杂质区， 侧壁间隔物和第一杂质区域，在第一杂质区域的表面处的第一硅化物膜，以及在栅极电极和第二杂质区域的表面处的第二硅化物膜。

公开(公告)号：US06010936A

公开(公告)日：2000-01-04

申请号：US979172

申请日：1997-11-26

申请人： Jeong-Hwan Son

发明人： Jeong-Hwan Son

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/7834 ,  H01L29/66545

摘要： A semiconductor device fabrication method and resulting device in which a gate insulating film is formed on a semiconductor substrate, a gate electrode is formed on the gate insulating film, a gate cap is formed on the gate electrode, a heavy density impurity region is formed in the substrate and outside the gate electrode, first side walls are formed on sides of the gate electrode, the gate cap and the gate insulating film. The substrate outside the gate insulating film is etched down to a portion having a highest impurity density, and a light doping region surrounding the heavy impurity region is formed in the substrate. The method and resulting device prevents a hot carrier from being injected into a gate oxide film or a side wall, and reduces the generation of a junction current leakage and a short channel.

摘要翻译： 一种在半导体衬底上形成栅极绝缘膜的半导体器件制造方法及其结果，在栅极绝缘膜上形成栅电极，在栅电极上形成栅极盖，形成重质杂质区 基板和栅电极外侧，第一侧壁形成在栅电极，栅极盖和栅极绝缘膜的侧面上。 栅绝缘膜外的基板被蚀刻到具有最高杂质浓度的部分，并且在该衬底中形成围绕重杂质区的光掺杂区域。 该方法和所得到的器件防止热载体注入栅极氧化膜或侧壁，并减少结电流泄漏和短通道的产生。

公开(公告)号：US5877068A

公开(公告)日：1999-03-02

申请号：US784062

申请日：1997-01-17

申请人： Ki Jae Huh ,  Jeong Hwan Son

发明人： Ki Jae Huh ,  Jeong Hwan Son

IPC分类号： H01L21/316 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76202

摘要： A method for forming an isolating layer in a semiconductor device includes the steps of forming a first material layer on an active layer having a major axis and a minor axis, forming a second material layer in a form of sidewall at sides of the first material layer in a direction of the major axis, and conducting field oxidation using the first and second material layers as masks to form the isolating layer.

摘要翻译： 在半导体器件中形成绝缘层的方法包括以下步骤：在具有长轴和短轴的有源层上形成第一材料层，在第一材料层的侧面形成侧壁形式的第二材料层 在长轴的方向上，并且使用第一和第二材料层作为掩模进行场氧化以形成隔离层。