公开(公告)号：US20130275456A1

公开(公告)日：2013-10-17

申请号：US13446679

申请日：2012-04-13

申请人： Jerry Cheng ,  Erik Jessen ,  Eric Hennings

发明人： Jerry Cheng ,  Erik Jessen ,  Eric Hennings

IPC分类号： G06F17/30

CPC分类号： G06F17/30864

摘要： Method, system, and programs for content search are disclosed. A user interface configured based on context information is presented within a host application. A plurality of selectable search results are then fetched based on the context information and a query received from a user through the user interface. An input associated with a selection of one or more selectable search results is received from the user through the user interface. The user interface is updated based on the plurality of selectable search results. In response to the selection, the one or more selected search results are provided to the host application with the context information.

摘要翻译： 公开了用于内容搜索的方法，系统和程序。 基于上下文信息配置的用户界面被呈现在主机应用内。 然后，基于上下文信息和通过用户界面从用户接收的查询来取出多个可选择的搜索结果。 通过用户界面从用户接收与一个或多个可选搜索结果的选择相关联的输入。 基于多个可选择的搜索结果更新用户界面。 响应于该选择，使用上下文信息将一个或多个所选择的搜索结果提供给主机应用。

公开(公告)号：US08862610B2

公开(公告)日：2014-10-14

申请号：US13446679

申请日：2012-04-13

申请人： Jerry Cheng ,  Erik Jessen ,  Eric Hennings

发明人： Jerry Cheng ,  Erik Jessen ,  Eric Hennings

IPC分类号： G06F17/00

CPC分类号： G06F17/30864

摘要： Method, system, and programs for content search are disclosed. A user interface configured based on context information is presented within a host application. A plurality of selectable search results are then fetched based on the context information and a query received from a user through the user interface. An input associated with a selection of one or more selectable search results is received from the user through the user interface. The user interface is updated based on the plurality of selectable search results. In response to the selection, the one or more selected search results are provided to the host application with the context information.

摘要翻译： 公开了用于内容搜索的方法，系统和程序。 基于上下文信息配置的用户界面被呈现在主机应用内。 然后，基于上下文信息和通过用户界面从用户接收的查询来取出多个可选择的搜索结果。 通过用户界面从用户接收与一个或多个可选搜索结果的选择相关联的输入。 基于多个可选择的搜索结果更新用户界面。 响应于该选择，使用上下文信息将一个或多个所选择的搜索结果提供给主机应用。

公开(公告)号：US06291887B1

公开(公告)日：2001-09-18

申请号：US09225220

申请日：1999-01-04

申请人： Fei Wang ,  Jerry Cheng ,  Todd Lukanc

发明人： Fei Wang ,  Jerry Cheng ,  Todd Lukanc

IPC分类号： H01L2348

CPC分类号： H01L21/76835 ,  H01L21/76807 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成第二低k电介质层。 将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中沟槽的过程中，通过采用只刻蚀第二低k电介质材料而不是第一低k电介质材料的蚀刻化学法来防止第一介质层中的底切。

公开(公告)号：US6153514A

公开(公告)日：2000-11-28

申请号：US225215

申请日：1999-01-04

申请人： Fei Wang ,  Jerry Cheng ,  Todd Lukanc

发明人： Fei Wang ,  Jerry Cheng ,  Todd Lukanc

IPC分类号： H01L21/311 ,  H01L21/312 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/02118 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/312 ,  H01L21/3124 ,  H01L21/7681

摘要： A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

摘要翻译： 在半导体器件布置中形成自对准双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氮化物蚀刻停止层，在氮化物蚀刻停止层上形成第二低k电介质层。 将沟槽蚀刻到第二低k介电层中，随后将通孔蚀刻到第一低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中的通孔时，通过采用蚀刻仅仅第一低k电介质材料而不是第二低k电介质材料的蚀刻化学法，由此防止了由过蚀刻引起的第二电介质层中的底切。

公开(公告)号：US08060510B2

公开(公告)日：2011-11-15

申请号：US12432172

申请日：2009-04-29

申请人： Joy Ghanekar ,  Jerry Cheng ,  Denis Hänikel

发明人： Joy Ghanekar ,  Jerry Cheng ,  Denis Hänikel

IPC分类号： G06F3/048 ,  G06F17/30

CPC分类号： G06F17/30241 ,  H04M1/27455 ,  H04M1/72572 ,  Y10S707/921

摘要： A search engine computer system is configured to produce an optimized display of maps especially useful in mobile handheld devices with comparatively small screens. The system factors in scoring functions, visibility, and empirical data on map levels to provide optimal map based results to users. This minimizes or avoids graphical results that overlap each other.

摘要翻译： 搜索引擎计算机系统被配置为产生在具有相对小的屏幕的移动手持设备中特别有用的地图的优化显示。 系统对于地图级别的功能，可见性和经验数据进行评分，以向用户提供最佳的基于地图的结果。 这最小化或避免彼此重叠的图形结果。

公开(公告)号：US06207576B1

公开(公告)日：2001-03-27

申请号：US09225543

申请日：1999-01-05

申请人： Fei Wang ,  Jerry Cheng

发明人： Fei Wang ,  Jerry Cheng

IPC分类号： H01L213065

CPC分类号： H01L21/7681 ,  H01L21/02118 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/312

摘要： A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A trench is etched into the second low k dielectric layer, followed by the etching of a via into the first low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the first low k dielectric material and not the second low k dielectric material.

摘要翻译： 在半导体器件布置中形成自对准双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氧化物蚀刻停止层，在氧化物蚀刻停止层上形成第二低k电介质层。 将沟槽蚀刻到第二低k介电层中，随后将通孔蚀刻到第一低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中的通孔时，通过采用蚀刻仅仅第一低k电介质材料而不是第二低k电介质材料的蚀刻化学法，由此防止了由过蚀刻引起的第二电介质层中的底切。

公开(公告)号：US06649525B1

公开(公告)日：2003-11-18

申请号：US10050485

申请日：2002-01-16

申请人： Khoi A. Phan ,  Jeffrey Erhardt ,  Jerry Cheng ,  Richard J. Bartlett ,  Anthony P. Coniglio ,  Wolfram Grundke ,  Carol M. Bradway ,  Daniel E. Sutton ,  Martin Mazur

发明人： Khoi A. Phan ,  Jeffrey Erhardt ,  Jerry Cheng ,  Richard J. Bartlett ,  Anthony P. Coniglio ,  Wolfram Grundke ,  Carol M. Bradway ,  Daniel E. Sutton ,  Martin Mazur

IPC分类号： H01L21461

CPC分类号： G03F7/16 ,  G03F7/30 ,  G03F7/40 ,  H01L21/0274 ,  H01L21/32139

摘要： Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein. The method may comprise employing an anti reflective coating prior to applying a photo resist coating in a semiconductor manufacturing process. Also disclosed are methodologies for exhausting resist residue during development via a rinsing fluid.

摘要翻译： 公开了用于减少半导体制造工艺中的抗蚀剂残留缺陷的方法和系统。 这些方法包括硬件，衬底，抗蚀剂，显影剂和工艺变量的适当调整，以便从半导体衬底结构去除抗蚀剂残留物，以减少其中的抗蚀剂残留缺陷。 该方法可以包括在半导体制造工艺中施加光致抗蚀剂涂层之前采用抗反射涂层。 还公开了通过冲洗流体在显影期间排出抗蚀剂残留物的方法。

公开(公告)号：US06235628B1

公开(公告)日：2001-05-22

申请号：US09225545

申请日：1999-01-05

申请人： Fei Wang ,  Jerry Cheng

发明人： Fei Wang ,  Jerry Cheng

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/76807

摘要： A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. An oxide etch stop layer is formed on the first low k dielectric layer, and a second low k dielectric layer is formed on the oxide etch stop layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Undercutting in the first dielectric layer is thereby prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

摘要翻译： 在半导体器件布置中形成双镶嵌结构的方法在下面的金属互连层（例如铜互连层）上形成第一低k电介质材料。 在第一低k电介质层上形成氧化物蚀刻停止层，在氧化物蚀刻停止层上形成第二低k电介质层。 将通孔蚀刻到第一低k电介质层中，然后将沟槽蚀刻到第二低k电介质层中。 第一和第二低k电介质材料彼此不同，使得它们对至少一种蚀刻剂化学物质具有不同的灵敏度。 因此，在蚀刻第二介质层中沟槽的过程中，通过采用只刻蚀第二低k电介质材料而不是第一低k电介质材料的蚀刻化学法来防止第一介质层中的底切。

公开(公告)号：US6107208A

公开(公告)日：2000-08-22

申请号：US90670

申请日：1998-06-04

申请人： Jerry Cheng ,  Fei Wang

发明人： Jerry Cheng ,  Fei Wang

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L21/05

CPC分类号： H01L21/76802 ,  H01L21/31116 ,  H01L21/76829 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002

摘要： In one embodiment, the present invention relates to a method of etching silicon nitride disposed over a copper containing layer by etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising from about 5 sccm to about 15 sccm of CHF.sub.3, about 5 sccm to about 15 sccm of nitrogen and about 80 sccm to about 120 sccm of a carrier gas. In another embodiment, the present invention relates to a method of processing a semiconductor substrate comprising silicon nitride disposed over a copper containing layer, involving etching at least a portion of the silicon nitride using a nitride etch gas mixture comprising CHF.sub.3, nitrogen and Ar.

摘要翻译： 在一个实施例中，本发明涉及一种通过使用包含约5sccm至约15sccm的CHF 3的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅而蚀刻设置在含铜层上方的氮化硅的方法，约 5sccm至约15sccm的氮气和约80sccm至约120sccm的载气。 在另一个实施例中，本发明涉及一种处理半导体衬底的方法，该半导体衬底包括设置在含铜层上的氮化硅，包括使用包含CHF 3，氮和Ar的氮化物蚀刻气体混合物蚀刻至少一部分氮化硅。

公开(公告)号：US6086777A

公开(公告)日：2000-07-11

申请号：US108783

申请日：1998-07-02

申请人： Jerry Cheng ,  Fei Wang

发明人： Jerry Cheng ,  Fei Wang

IPC分类号： C23F4/00 ,  H01L21/3213 ,  H01L21/768 ,  C23F1/10

CPC分类号： H01L21/7684 ,  C23F4/00 ,  H01L21/32136 ,  H01L21/76843 ,  H01L21/76858 ,  H01L21/76873

摘要： In one embodiment, the present invention relates to a method of etching tantalum disposed over a dielectric layer, involving etching at least a portion of the tantalum using a tantalum etch gas mixture containing from about 300 sccm to about 400 sccm of CF.sub.4 and about 200 sccm to about 600 sccm of oxygen at a temperature from about 100.degree. C. to about 150.degree. C. under a pressure from about 1 torr to about 1.5 torr. In another embodiment, the present invention relates to a method of etching at least a portion of a tantalum barrier layer, the tantalum barrier layer at least partially surrounding a copper or copper alloy interconnect, involving etching at least a portion of the tantalum barrier layer using a tantalum etch gas mixture containing from about 300 sccm to about 400 sccm of CF.sub.4 and about 200 sccm to about 600 sccm of oxygen.

摘要翻译： 在一个实施例中，本发明涉及蚀刻设置在电介质层上的钽的方法，包括使用包含约300sccm至约400sccm的CF 4和约200sccm的钽蚀刻气体混合物来蚀刻钽的至少一部分 至约600sccm的氧气，在约1托至约1.5托的压力下在约100℃至约150℃的温度下进行。 在另一个实施例中，本发明涉及一种蚀刻钽阻挡层的至少一部分的方法，所述钽阻挡层至少部分地围绕铜或铜合金互连，包括用钽蚀刻至少一部分钽阻挡层，使用 包含约300sccm至约400sccm的CF 4和约200sccm至约600sccm的氧的钽蚀刻气体混合物。