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    Field Effect Transistor Arrangement
    1.
    发明申请
    Field Effect Transistor Arrangement 审中-公开
    场效应晶体管布置

    公开(公告)号：US20080197384A1

    公开(公告)日：2008-08-21

    申请号：US12035195

    申请日：2008-02-21

    申请人： Jessica Hartwich ,  Lars Dreeskornfeld ,  Gernot Steinlesberger

    发明人： Jessica Hartwich ,  Lars Dreeskornfeld ,  Gernot Steinlesberger

    IPC分类号： H01L29/423 ,  H01L21/336

    CPC分类号： H01L29/78618 ,  H01L29/41783 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer, and also a gate region having an electrically insulating gate layer and an electrically conductive gate layer, which adjoins the channel region or is arranged at a distance from the latter and which extends at least partly along the channel region, wherein the source region and the drain region are in each case produced from electrically conductive carbon, and wherein the channel region is produced from strained silicon.

    摘要翻译： 场效应晶体管布置包括电绝缘层，源极区，漏极区和布置在源极区和漏极区之间的沟道区，其中源区，漏区和沟道区分别布置在或超过 电绝缘层，以及具有电绝缘栅极层和导电栅极层的栅极区域，其邻接沟道区域或者与沟道区域相距一定距离并且至少部分地沿沟道区域延伸，其中， 源极区域和漏极区域在每种情况下由导电碳生成，并且其中沟道区域由应变硅产生。

    Integrated circuit and method of forming an integrated circuit
    2.
    发明申请
    Integrated circuit and method of forming an integrated circuit 审中-公开
    集成电路和形成集成电路的方法

    公开(公告)号：US20090086523A1

    公开(公告)日：2009-04-02

    申请号：US11904783

    申请日：2007-09-28

    申请人： Jessica Hartwich ,  Lars Dreeskornfeld

    发明人： Jessica Hartwich ,  Lars Dreeskornfeld

    IPC分类号： G11C5/06 ,  H01L21/336

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/785

    摘要： An integrated circuit comprises a memory cell array portion and a support circuitry portion. The memory cell array portion comprises at least one bitline and at least one wordline, which is disposed above the bitline. The support circuitry portion comprises a FinFET comprising a gate electrode. An upper side of a portion of the gate electrode is disposed at the same height as an upper side of a portion of the bitline. A method of manufacturing an integrated circuit comprises the steps of forming a memory cell array and forming a support circuitry. The step of forming the memory cell array comprises forming a bitline and forming a wordline disposed above the bitline. The step of forming the support circuitry comprises forming a FinFET. The step of forming the FinFET comprises forming a gate electrode, an upper side of a portion of the gate electrode being formed at the same height as an upper side of a portion of the bitline.

    摘要翻译： 集成电路包括存储单元阵列部分和支持电路部分。 存储单元阵列部分包括设置在位线上方的至少一个位线和至少一个字线。 支撑电路部分包括包括栅电极的FinFET。 栅电极的一部分的上侧设置在与位线的一部分的上侧相同的高度。 一种制造集成电路的方法包括以下步骤：形成存储单元阵列并形成支持电路。 形成存储单元阵列的步骤包括形成位线并形成设置在位线上方的字线​​。 形成支撑电路的步骤包括形成FinFET。 形成FinFET的步骤包括形成栅电极，栅电极的一部分的上侧形成在与位线的一部分的上侧相同高度处。

    METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER
    3.
    发明申请
    METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER 有权
    制造集成电路的方法，其中包括具有栅极间隔的FET

    公开(公告)号：US20100078711A1

    公开(公告)日：2010-04-01

    申请号：US12242039

    申请日：2008-09-30

    申请人： Matthias Goldbach ,  Jessica Hartwich ,  Lars Dreeskornfeld ,  Arnd Scholz ,  Tobias Mono

    发明人： Matthias Goldbach ,  Jessica Hartwich ,  Lars Dreeskornfeld ,  Arnd Scholz ,  Tobias Mono

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

    摘要翻译： 一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。 一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。 薄片凹进。 翅片由薄片的中心部分形成。 翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。 形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。 栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

    Method of manufacturing integrated circuits including a FET with a gate spacer and a fin
    5.
    发明授权
    Method of manufacturing integrated circuits including a FET with a gate spacer and a fin 有权
    制造集成电路的方法，该集成电路包括具有栅极间隔物和鳍的FET

    公开(公告)号：US07863136B2

    公开(公告)日：2011-01-04

    申请号：US12242039

    申请日：2008-09-30

    申请人： Matthias Goldbach ,  Jessica Hartwich ,  Lars Dreeskornfeld ,  Arnd Scholz ,  Tobias Mono

    发明人： Matthias Goldbach ,  Jessica Hartwich ,  Lars Dreeskornfeld ,  Arnd Scholz ,  Tobias Mono

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.

    摘要翻译： 一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。 一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。 薄片凹进。 翅片由薄片的中心部分形成。 翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。 形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。 栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

    Fin field effect transistor memory cell
    8.
    发明申请
    Fin field effect transistor memory cell 审中-公开
    Fin场效应晶体管存储单元

    公开(公告)号：US20060001058A1

    公开(公告)日：2006-01-05

    申请号：US11157496

    申请日：2005-06-20

    申请人： Lars Dreeskornfeld ,  Jessica Hartwich ,  Franz Hofmann ,  Johannes Kretz ,  Michael Specht

    发明人： Lars Dreeskornfeld ,  Jessica Hartwich ,  Franz Hofmann ,  Johannes Kretz ,  Michael Specht

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/42384 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

    摘要： A fin field effect transistor memory cell having a first and a second source/drain region, a gate region, a semiconductor fin having a channel region between the first and the second source/drain region, a charge storage layer configured as a trapping layer arranged at least partly on the gate region, and a word line region on at least one part of the charge storage layer. The charge storage layer is set up such that electrical charge carriers can be selectively introduced into the charge storage layer or be removed therefrom by applying predetermined electrical potentials to the fin field effect transistor memory cell.

    摘要翻译： 具有第一和第二源极/漏极区域的栅极场效应晶体管存储单元，栅极区域，具有在第一和第二源极/漏极区域之间的沟道区域的半导体鳍片，被配置为俘获层的电荷存储层， 至少部分地在栅极区域上，以及电荷存储层的至少一部分上的字线区域。 电荷存储层被设置成使得电荷载流子可以选择性地引入电荷存储层中，或者通过向鳍式场效应晶体管存储单元施加预定的电位而将其移除。

    Integrated circuit arrangement comprising a capacitor, and production method
    10.
    发明申请
    Integrated circuit arrangement comprising a capacitor, and production method 有权
    包括电容器的集成电路装置和制造方法

    公开(公告)号：US20060003526A1

    公开(公告)日：2006-01-05

    申请号：US10529990

    申请日：2003-10-10

    申请人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rosner ,  Thomas Schulz

    发明人： Ralf Brederlow ,  Jessica Hartwich ,  Christian Pacha ,  Wolfgang Rosner ,  Thomas Schulz

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

    摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

    摘要翻译： 集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。 电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。 近电极区域是单晶体并且包含多个网状物。 或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。 厚的绝缘区域比控制电极绝缘区域厚。 控制电极含有与远电极区域相同的材料。