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13 条记录 (耗时 0.017 秒)

    Field Effect Transistor Arrangement
    1.
    发明申请
    Field Effect Transistor Arrangement 审中-公开
    场效应晶体管布置

    公开(公告)号：US20080197384A1

    公开(公告)日：2008-08-21

    申请号：US12035195

    申请日：2008-02-21

    申请人： Jessica Hartwich ,  Lars Dreeskornfeld ,  Gernot Steinlesberger

    发明人： Jessica Hartwich ,  Lars Dreeskornfeld ,  Gernot Steinlesberger

    IPC分类号： H01L29/423 ,  H01L21/336

    CPC分类号： H01L29/78618 ,  H01L29/41783 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78654

    摘要： A field effect transistor arrangement includes an electrically insulating layer, a source region, a drain region and a channel region arranged between source region and drain region, wherein the source region, the drain region and the channel region are in each case arranged on or above the electrically insulating layer, and also a gate region having an electrically insulating gate layer and an electrically conductive gate layer, which adjoins the channel region or is arranged at a distance from the latter and which extends at least partly along the channel region, wherein the source region and the drain region are in each case produced from electrically conductive carbon, and wherein the channel region is produced from strained silicon.

    摘要翻译： 场效应晶体管布置包括电绝缘层，源极区，漏极区和布置在源极区和漏极区之间的沟道区，其中源区，漏区和沟道区分别布置在或超过 电绝缘层，以及具有电绝缘栅极层和导电栅极层的栅极区域，其邻接沟道区域或者与沟道区域相距一定距离并且至少部分地沿沟道区域延伸，其中， 源极区域和漏极区域在每种情况下由导电碳生成，并且其中沟道区域由应变硅产生。

    Method for manufacturing a layer arrangement and layer arrangement
    2.
    发明授权
    Method for manufacturing a layer arrangement and layer arrangement 有权
    制造层布置和层布置的方法

    公开(公告)号：US07807563B2

    公开(公告)日：2010-10-05

    申请号：US11786770

    申请日：2007-04-12

    申请人： Zvonimir Gabric ,  Werner Pamler ,  Guenther Schindler ,  Gernot Steinlesberger ,  Andreas Stich ,  Martin Traving ,  Eugen Unger

    发明人： Zvonimir Gabric ,  Werner Pamler ,  Guenther Schindler ,  Gernot Steinlesberger ,  Andreas Stich ,  Martin Traving ,  Eugen Unger

    IPC分类号： H01L23/58

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a method for manufacturing a layer arrangement, a plurality of electrically conductive structures are embedded in a substrate. Material of the substrate is removed at least between adjacent electrically conductive structures. An interlayer is formed on at least one portion of sidewalls of each of the electrically conductive structures. A first layer is formed on the interlayer where an upper partial region of the interlayer remaining free of a covering with the first layer. An electrically insulating second layer is formed selectively on that partial region of the interlayer which is free of the first layer, in such a way that the electrically insulating second layer bridges adjacent electrically conductive structures such that air gaps are formed between adjacent electrically conductive structures.

    摘要翻译： 在制造层布置的方法中，多个导电结构嵌入基板中。 至少在相邻的导电结构之间去除衬底的材料。 在每个导电结构的侧壁的至少一部分上形成中间层。 第一层形成在中间层上，其中层间的上部分区域保留没有覆盖物与第一层。 选择性地在中间层的不含第一层的部分区域上形成电绝缘的第二层，使得电绝缘的第二层桥接相邻的导电结构，使得在相邻的导电结构之间形成气隙。

    COMMUNICATION SYSTEM
    3.
    发明申请
    COMMUNICATION SYSTEM 失效
    具有纳米结构的电路和用于生产纳米结构的接触连接的方法

    公开(公告)号：US20090213830A1

    公开(公告)日：2009-08-27

    申请号：US11577070

    申请日：2005-10-11

    申请人： Georg Duesberg ,  Franz Kreupl ,  Robert Seidel ,  Gernot Steinlesberger

    发明人： Georg Duesberg ,  Franz Kreupl ,  Robert Seidel ,  Gernot Steinlesberger

    IPC分类号： H04J3/00 ,  H04B1/38 ,  G08B13/14

    CPC分类号： H01L51/0048 ,  B82Y10/00 ,  H01L51/0021

    摘要： A communication system is disclosed. In one embodiment, the communication system includes a communication device set up to execute a process, configured to put itself into an activated state or into a deactivated state at alternate times, receive time information in a first operating state of the activated state, take the received time information as a basis for ascertaining the later time at which useful information is transmitted to the communication device, receive the useful information at the later time in a second operating state of the activated state. Individual components of the communication device are able to be put into an activated state or into a deactivated state independently of one another.

    摘要翻译： 公开了一种电路。 该电路包括由基本上碳层形成的至少一个纳米结构和碳互连，其中纳米结构和碳互连彼此直接耦合。

    Process for producing ultrathin homogenous metal layers
    5.
    发明授权
    Process for producing ultrathin homogenous metal layers 有权
    生产超薄均质金属层的方法

    公开(公告)号：US06946386B2

    公开(公告)日：2005-09-20

    申请号：US10854759

    申请日：2004-05-25

    申请人： Gernot Steinlesberger ,  Manfred Engelhardt ,  Eugen Unger

    发明人： Gernot Steinlesberger ,  Manfred Engelhardt ,  Eugen Unger

    IPC分类号： C23C18/31 ,  C23C28/02 ,  H01L21/4763

    CPC分类号： C23C18/31 ,  C23C28/023

    摘要： A method of forming an ultrathin homogenous metal layer that serves as base metallization for formation of contact locations and/or contact pads and/or wirings of an integrated electronic component. The method includes the steps of depositing a first metal layer on a substrate at least in regions, and producing a second metal layer on the first metal layer at least in regions, component(s) of the second metal layer have a more positive redox potential than component(s) of the first metal layer, wherein ultrathin homogenous deposition of the second metal layer is effected by wet-chemical, current-free, electrochemical redox processes by element exchange from one or more metal salts as oxidant with at least a top metal atomic layer of the first metal layer as reductant.

    摘要翻译： 形成用于形成集成电子部件的接触位置和/或接触焊盘和/或布线的基底金属化的超薄均匀金属层的方法。 该方法包括以下步骤：至少在区域中在衬底上沉积第一金属层，并且至少在区域中在第一金属层上产生第二金属层，第二金属层的组分具有更正的氧化还原电位 其中第二金属层的超薄均匀沉积通过湿化学，无电流的电化学氧化还原过程通过元素交换从一种或多种金属盐作为氧化剂与至少一个顶部进行 第一金属层的金属原子层作为还原剂。

    Memory buffer and method for buffering data
    8.
    发明申请
    Memory buffer and method for buffering data 审中-公开
    内存缓冲区和缓冲数据的方法

    公开(公告)号：US20080126624A1

    公开(公告)日：2008-05-29

    申请号：US11604665

    申请日：2006-11-27

    申请人： Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders ,  Gernot Steinlesberger ,  Maurizio Skerlj ,  Dirk Scheideler ,  Georg Braun ,  Steve Wood ,  Richard Johannes Luyken

    发明人： Edoardo Prete ,  Hans-Peter Trost ,  Anthony Sanders ,  Gernot Steinlesberger ,  Maurizio Skerlj ,  Dirk Scheideler ,  Georg Braun ,  Steve Wood ,  Richard Johannes Luyken

    IPC分类号： G06F3/00

    CPC分类号： G11C7/1051 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/106

    摘要： A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

    摘要翻译： 存储器缓冲器包括可连接到存储器控制器和存储器缓冲器中的至少一个的第一异步锁存链接口，连接到存储器件的第二数据接口以及包括缓冲器和处理器的电路，该电路耦合到 第一和第二接口，使得数据可以在第一接口和缓冲器之间以及第二接口和缓冲器之间传递，使得处理器能够处理从第一接口到第二接口的数据中的至少一个 以及根据数据处理功能的来自第二接口的数据，其中处理器的数据处理功能可以通过经由存储器缓冲器的接口接收的编程信号来改变。