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公开(公告)号：US09532462B2
公开(公告)日：2016-12-27
申请号：US13512271
申请日：2010-11-25
Applicant: Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
Inventor： Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
CPC classification number: H05K3/101 , H05K1/02 , H05K1/0353 , H05K1/092 , H05K3/02 , H05K3/108 , H05K3/20 , H05K2201/0376 , H05K2203/0278
Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.
Abstract translation: 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。
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公开(公告)号：US08956962B2
公开(公告)日：2015-02-17
申请号：US13242331
申请日：2011-09-23
Applicant: Young-Jae Lee , Kyoung Jong Yoo , Jin Su Kim , Jun Lee , Yong In Lee , JunBo Yoon , JeongHo Yeon , Joo-Hyung Lee , Jeong Oen Lee
Inventor： Young-Jae Lee , Kyoung Jong Yoo , Jin Su Kim , Jun Lee , Yong In Lee , JunBo Yoon , JeongHo Yeon , Joo-Hyung Lee , Jeong Oen Lee
IPC: H01L21/40 , H01L21/033 , B82Y10/00
CPC classification number: H01L21/0337 , B82Y10/00 , H01L21/0338 , Y10S438/947
Abstract: A method for fabricating a large-area nanoscale pattern includes: forming multilayer main thin films isolated by passivation layers; patterning a first main thin film to form a first main pattern; forming a first spacer pattern with respect to the first main pattern; and forming a second main pattern by transferring the first spacer pattern onto a second main thin film. By using multilayer main thin films isolated by different passivation films, spacer lithography capable of reducing a pattern pitch can be repetitively performed, and the pattern pitch is repetitively reduced without shape distortion after formation of micrometer-scale patterns, thereby forming nanometer-scale fine patterns uniformly over a wide area.
Abstract translation: 一种制造大面积纳米级图案的方法包括：形成由钝化层隔离的多层主薄膜; 图案化第一主薄膜以形成第一主图案; 相对于所述第一主图形形成第一间隔图案; 以及通过将第一间隔图案转印到第二主薄膜上而形成第二主图案。 通过使用由不同钝化膜分离的多层主薄膜，可以重复地进行能够减小图案间距的间隔光刻，并且在形成微米尺度图案之后，图案间距重复减小而没有形状变形，从而形成纳米级精细图案 均匀地在广泛的地区。
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公开(公告)号：US20130112463A1
公开(公告)日：2013-05-09
申请号：US13512271
申请日：2010-11-25
Applicant: Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
Inventor： Yeong Uk Seo , Sung Woon Yoon , Jin Su Kim , Myoung Hwa Nam , Sang Myung Lee , Chi Hee Ahn
CPC classification number: H05K3/101 , H05K1/02 , H05K1/0353 , H05K1/092 , H05K3/02 , H05K3/108 , H05K3/20 , H05K2201/0376 , H05K2203/0278
Abstract: The present invention provides a structure of a printed circuit board and a manufacturing method thereof. The method includes: (a) forming a circuit pattern on an insulating layer in which a seed layer is formed; (b) embedding the circuit pattern into the insulating layer by a press method; and (c) removing the seed layer. According to the present invention, a fine pattern may be formed without occurring alignment problem by forming a circuit pattern directly on an insulating layer and reliability of the formed fine pattern may be increased by performing a process of embedding protruded circuits into the insulating layer. In addition, possibility of inferior circuit occurring due to ion migration between adjacent circuits may be reduced by performing over-etching a circuit layer to be lower than a surface of the insulating layer during the etching process of removing a seed layer.
Abstract translation: 本发明提供一种印刷电路板的结构及其制造方法。 该方法包括：（a）在形成种子层的绝缘层上形成电路图形; （b）通过压制方法将电路图案嵌入绝缘层; 和（c）去除种子层。 根据本发明，可以通过在绝缘层上直接形成电路图案而形成不发生取向问题的精细图案，并且通过执行将突出电路嵌入绝缘层中的工艺可以提高形成的精细图案的可靠性。 此外，通过在去除种子层的蚀刻工艺期间，通过在电路层上过度蚀刻比低于绝缘层的表面的电路层，由于相邻电路之间的离子迁移而发生劣质电路的可能性可能会降低。
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4.发明申请SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME 失效半导体封装及其制造方法和具有该半导体元件的半导体封装模块公开(公告)号：US20130105955A1
公开(公告)日：2013-05-02
申请号：US13361144
申请日：2012-01-30
Applicant: Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
Inventor： Jin Su Kim , Ji Man Ryu , Soon Gyu Yim
IPC: H01L23/495 , H01L21/50 , H01L23/48
CPC classification number: H01L24/83 , H01L23/3121 , H01L23/49503 , H01L23/49513 , H01L23/49524 , H01L23/49531 , H01L23/49575 , H01L24/32 , H01L24/48 , H01L24/49 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2924/00014 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2924/18301 , H01L2924/19107 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
Abstract: Disclosed herein is a semiconductor chip, including: a first substrate having a concave formed on one surface thereof and an opening formed on a bottom surface of the concave; a second substrate contacting the other surface of the first substrate; and a semiconductor chip mounted in the concave.
Abstract translation: 本文公开了一种半导体芯片，包括：在其一个表面上形成有凹部的第一基板和形成在凹部的底表面上的开口; 与第一基板的另一个表面接触的第二基板; 以及安装在凹部中的半导体芯片。
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公开(公告)号：US20130062106A1
公开(公告)日：2013-03-14
申请号：US13512748
申请日：2010-11-26
Applicant: Jin Su Kim , Duk Nam Kim , Jae Hyun Ahn , Sang Myung Lee , Yeong Uk Seo , Chi Hee Ahn , Sung Woon Yoon , Myoung Hwa Nam
Inventor： Jin Su Kim , Duk Nam Kim , Jae Hyun Ahn , Sang Myung Lee , Yeong Uk Seo , Chi Hee Ahn , Sung Woon Yoon , Myoung Hwa Nam
CPC classification number: H05K3/4658 , H05K3/205 , H05K3/4007 , H05K3/4647 , H05K2203/0108 , Y10T29/49155
Abstract: A structure of a printed circuit board and a method of manufacturing the same are provided. The manufacturing method includes a first step of forming at least one connecting bump on first circuit patterns and forming a first insulating layer to form an inner circuit board, a second step of processing a second insulating layer with a metal seed layer formed thereon using a mold to form second circuit patterns so as to construct an outer circuit board, and a third step of aligning the inner circuit board and the outer circuit board with each other and laminating the inner circuit board and the outer circuit board. Accordingly, a structure of a high-density high-reliability printed circuit board having a circuit embedded in an insulating layer can be provided. A seed layer forming process for forming an outmost circuit can be removed by using an insulating layer combined with a seed layer. In addition, a conductive structure in the form of a connecting bump is formed, and thus a complicated process of forming a via-hole and filling the via-hole with a conductive material is not required. Furthermore, a process of grinding the surface of the filled conductive material is removed so as to remarkably decrease a circuit error rate.
Abstract translation: 提供一种印刷电路板的结构及其制造方法。 该制造方法包括：在第一电路图案上形成至少一个连接凸块并形成第一绝缘层以形成内部电路板的第一步骤;使用模具处理其上形成有金属晶种层的第二绝缘层的第二步骤 以形成第二电路图案以构成外部电路板，以及将内部电路板和外部电路板彼此对准并层压内部电路板和外部电路板的第三步骤。 因此，可以提供具有嵌入在绝缘层中的电路的高密度高可靠性印刷电路板的结构。 可以通过使用与种子层结合的绝缘层来去除用于形成最外层电路的籽晶层形成工艺。 此外，形成连接凸块形式的导电结构，因此不需要形成通孔并且用导电材料填充通孔的复杂工艺。 此外，去除了填充的导电材料的表面的研磨过程，以显着降低电路错误率。
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Patent Agency Ranking
公开(公告)号：US20120075830A1
公开(公告)日：2012-03-29
申请号：US13240028
申请日：2011-09-22
Applicant: YOUNG-JAE LEE , Jin Su Kim , Jun Lee
Inventor： YOUNG-JAE LEE , Jin Su Kim , Jun Lee
CPC classification number: G02B5/3058
Abstract: Provided is a wire grid polarizer and a backlight unit using the wire grid polarizer. The wire grid polarizer comprises a first grid layer thrilled on a substrate and provided with at least one of a first grid pattern, and a second grid layer formed on the first grid pattern and provided with at least one of a second grid pattern made of metal material wherein the first grid layer is made of high molecular substance having a lower refraction index than that of the substrate.According to the present invention, by forming a first grid pattern on a substrate using a high molecular substance layer and by forming a metal grid pattern on the first grid pattern, transmission rates of respective wavelengths depending on light angles of incident light are controlled and thereby minimizing color variations depending on view angle.
Abstract translation: 提供了使用线栅偏振器的线栅偏振器和背光单元。 线栅偏振器包括在衬底上激发的第一栅格层，并且设置有形成在第一栅格图案上的第一栅格图案和第二栅格层中的至少一个，并且设置有由金属制成的第二栅格图案中的至少一个 材料，其中第一栅格层由具有比衬底的折射率低的折射率的高分子物质制成。 根据本发明，通过使用高分子物质层在基板上形成第一栅格图案，并且在第一栅格图案上形成金属栅格图案，控制根据入射光的光角度的各波长的透射率，由此 最小化取决于视角的颜色变化。
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7.发明授权Stacked semiconductor chip package having external terminal pads and stackable chips having a protection layer 失效具有外部端子焊盘的堆叠半导体芯片封装和具有保护层的可堆叠芯片公开(公告)号：US06188129B1
公开(公告)日：2001-02-13
申请号：US09046136
申请日：1998-03-23
Applicant: Kyung Wook Paik , Jin Su Kim , Hyoung Soo Ko
Inventor： Kyung Wook Paik , Jin Su Kim , Hyoung Soo Ko
IPC: H01L2302
CPC classification number: H01L25/0657 , H01L2224/16 , H01L2224/16108 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551
Abstract: The stackable semiconductor chip includes a semiconductor chip having pads on an upper surface thereof, and an adhesive formed on lateral surfaces of the semiconductor chip. A first insulation layer is formed over the upper surface of the semiconductor chip and the adhesive, and defines a plurality of through holes which expose the pads. Metal lines, formed on the first insulation layer, are connected to a respective one of the pads via a respective one of the through holes. A protective layer is formed on the metal lines and the first insulation layer. A plurality of stackable semiconductor chips are stacked by disposing double-sided adhesive between the stackable semiconductor chips. Then a plurality of external terminal pads are formed on one of the lateral surfaces of the stack of stackable semiconductor chips. Each external terminal pad is electrically connected to at least one of the metal lines in one of the stackable semiconductor chips. Next, a solder ball is formed on each of the plurality of external terminal pads to produce a stacked semiconductor chip package.
Abstract translation: 可堆叠半导体芯片包括其上表面具有焊盘的半导体芯片和形成在半导体芯片的侧表面上的粘合剂。 第一绝缘层形成在半导体芯片和粘合剂的上表面上，并且限定了暴露焊盘的多个通孔。 形成在第一绝缘层上的金属线通过相应的一个通孔连接到相应的一个焊盘。 在金属线和第一绝缘层上形成保护层。 通过在可堆叠的半导体芯片之间设置双面粘合剂来堆叠多个可堆叠的半导体芯片。 然后，在堆叠的可堆叠半导体芯片的堆叠的一个侧表面上形成多个外部端子焊盘。 每个外部终端焊盘电连接到一个可堆叠半导体芯片中的至少一个金属线。 接下来，在多个外部端子焊盘中的每一个上形成焊球以产生堆叠的半导体芯片封装。
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公开(公告)号：US09491866B2
公开(公告)日：2016-11-08
申请号：US13809083
申请日：2011-07-07
Applicant: Sang Myung Lee , Byeong Ho Kim , Jin Su Kim , Myoung Hwa Nam , Yeong Uk Seo , Sung Woon Yoon
Inventor： Sang Myung Lee , Byeong Ho Kim , Jin Su Kim , Myoung Hwa Nam , Yeong Uk Seo , Sung Woon Yoon
CPC classification number: H05K3/062 , H05K3/0026 , H05K3/0032 , H05K3/02 , H05K3/045 , H05K3/108 , H05K3/465 , H05K2203/0554 , H05K2203/0557 , Y10T29/49167
Abstract: Provided is a method for manufacturing a printed circuit board. The method for manufacturing a printed circuit board includes preparing an insulation board, irradiating a laser onto a graytone mask to each a surface of the insulation board, thereby forming a circuit pattern groove and a via hole at the same time, and filling the circuit pattern groove and the via hole to form a buried circuit pattern and the via. Thus, the circuit pattern groove and the via hole may be formed using the graytone mask at the same time without perfolining a separate process for forming the via hole. Therefore, the manufacturing process may be simplified to reduce the manufacturing costs.
Abstract translation: 提供一种印刷电路板的制造方法。 制造印刷电路板的方法包括制备绝缘板，将激光照射到灰蒙蒙掩模到绝缘板的每个表面上，从而同时形成电路图案槽和通孔，并填充电路图案 沟槽和通孔形成掩埋电路图案和通孔。 因此，电路图案槽和通孔可以同时使用灰蒙版掩模形成，而不需要单独的用于形成通孔的工艺。 因此，可以简化制造过程以降低制造成本。
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公开(公告)号：US09488764B2
公开(公告)日：2016-11-08
申请号：US13240028
申请日：2011-09-22
Applicant: Young-Jae Lee , Jin Su Kim , Jun Lee
Inventor： Young-Jae Lee , Jin Su Kim , Jun Lee
IPC: G02B5/30
CPC classification number: G02B5/3058
Abstract: Provided are a wire grid polarizer and a backlight unit using the wire grid polarizer. The wire grid polarizer comprises a first grid layer formed on a substrate and provided with at least one of a first grid pattern, and a second grid layer formed on the first grid pattern and provided with at least one of a second grid pattern made of metal material wherein the first grid layer is made of high molecular substance having a lower refraction index than that of the substrate. By forming a first grid pattern on a substrate using a high molecular substance layer and by forming a metal grid pattern on the first grid pattern, transmission rates of respective wavelengths depending on light angles of incident light are controlled and thereby minimize color variations depending on view angle.
Abstract translation: 提供了使用线栅偏振器的线栅偏振器和背光单元。 线栅偏振器包括形成在基板上的第一栅格层，并且设置有形成在第一栅格图案上的第一栅格图案和第二栅格层中的至少一个，并且设置有由金属制成的第二栅格图案中的至少一个 材料，其中第一栅格层由具有比衬底的折射率低的折射率的高分子物质制成。 通过使用高分子物质层在基板上形成第一栅格图案，并且通过在第一栅格图案上形成金属栅格图案，控制取决于入射光的光角的各波长的透射率，从而根据视图最小化颜色变化 角度。
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公开(公告)号：US09265161B2
公开(公告)日：2016-02-16
申请号：US12956545
申请日：2010-11-30
Applicant: Chi Hee Ahn , Sang Myung Lee , Yeong Uk Seo , Jin Su Kim , Sung Woon Yoon , Myoung Hwa Nam
Inventor： Chi Hee Ahn , Sang Myung Lee , Yeong Uk Seo , Jin Su Kim , Sung Woon Yoon , Myoung Hwa Nam
CPC classification number: H05K3/465 , H05K3/0032 , H05K3/045 , H05K3/107 , H05K3/184 , H05K3/4661 , H05K2203/054 , Y10T29/49124 , Y10T29/49155
Abstract: An embedded PCB, a multi-layer PCB using the embedded PCB, and a method of manufacturing the same are provided. The method of manufacturing an embedded PCB includes a first step of patterning an insulating layer on which a photoresist layer is formed using a laser such that parts of the insulating layer are selectively etched to form a circuit pattern region and a second step of filling the circuit pattern region with a plating material to form a circuit pattern. Accordingly, the method of manufacturing an embedded PCB can simultaneously or sequentially etch a photoresist layer and an insulating layer using a laser to form a circuit pattern so as to obtain a micro pattern and simplify a manufacturing process and achieve alignment accuracy in construction of a multi-layer PCB using the embedded PCB to thereby improve product reliability and yield.
Abstract translation: 提供嵌入式PCB，使用嵌入式PCB的多层PCB及其制造方法。 制造嵌入式PCB的方法包括：使用激光使绝缘层图案化的第一步骤，使得绝缘层的一部分被选择性地蚀刻以形成电路图案区域;以及第二步骤， 图案区域与电镀材料形成电路图案。 因此，制造嵌入式PCB的方法可以使用激光器同时或顺序地蚀刻光致抗蚀剂层和绝缘层，以形成电路图案，从而获得微图案并简化制造工艺，并实现多层结构的对准精度 使用嵌入式PCB的PCB层，从而提高产品的可靠性和产量。
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