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    Recyclable stamp device and recyclable stamp process for wafer bond
    1.
    发明申请
    Recyclable stamp device and recyclable stamp process for wafer bond 有权
    可回收邮票装置和可回收的贴片过程

    公开(公告)号：US20080157406A1

    公开(公告)日：2008-07-03

    申请号：US12003408

    申请日：2007-12-26

    Applicant: Jiunn Chen ,  Meng-Jen Wang

    Inventor： Jiunn Chen ,  Meng-Jen Wang

    IPC: H01L23/544 ,  H01L21/30

    CPC classification number: H01L21/50 ,  B81C1/00269 ,  B81C2201/0191 ,  H01L21/6835 ,  H01L23/10 ,  H01L23/544 ,  H01L2221/68359 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/00

    Abstract: A recyclable stamp device and a recyclable stamp process for wafer bond are provided. The recyclable stamp device includes a substrate, a protective layer, a stack film structure and a cap. The protective layer is disposed on the substrate. An opening is positioned at the substrate and the protective layer to expose the substrate. The stack film structure includes an adhesion layer, a stress control layer and a wafer bond alignment mark layer. The adhesion layer is disposed on the protective layer and the exposed substrate. The stress control layer is disposed on the adhesion layer. The wafer bond alignment mark layer is disposed on the stress control layer. The wafer bond alignment mark layer includes an alignment mark at a side of the opening. The cap has a capping portion disposed on the wafer bond alignment mark layer corresponding to the opening.

    Abstract translation: 提供了一种用于晶片接合的可循环印模装置和可循环印模工艺。 可回收印章装置包括基板，保护层，叠层膜结构和盖。 保护层设置在基板上。 开口位于衬底和保护层上以露出衬底。 叠层膜结构包括粘合层，应力控制层和晶片接合对准标记层。 粘合层设置在保护层和暴露的基底上。 应力控制层设置在粘合层上。 晶片接合对准标记层设置在应力控制层上。 晶片接合对准标记层包括在开口侧的对准标记。 盖具有设置在与开口对应的晶片接合对准标记层上的封盖部分。

    Recyclable stamp device and recyclable stamp process for wafer bond
    2.
    发明授权
    Recyclable stamp device and recyclable stamp process for wafer bond 有权
    可回收邮票装置和可回收的贴片过程

    公开(公告)号：US07696060B2

    公开(公告)日：2010-04-13

    申请号：US12003408

    申请日：2007-12-26

    Applicant: Jiunn Chen ,  Meng-Jen Wang

    Inventor： Jiunn Chen ,  Meng-Jen Wang

    IPC: H01L21/76

    CPC classification number: H01L21/50 ,  B81C1/00269 ,  B81C2201/0191 ,  H01L21/6835 ,  H01L23/10 ,  H01L23/544 ,  H01L2221/68359 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/16152 ,  H01L2924/16235 ,  H01L2924/00

    Abstract: A recyclable stamp device and a recyclable stamp process for wafer bond are provided. The recyclable stamp device includes a substrate, a protective layer, a stack film structure and a cap. The protective layer is disposed on the substrate. An opening is positioned at the substrate and the protective layer to expose the substrate. The stack film structure includes an adhesion layer, a stress control layer and a wafer bond alignment mark layer. The adhesion layer is disposed on the protective layer and the exposed substrate. The stress control layer is disposed on the adhesion layer. The wafer bond alignment mark layer is disposed on the stress control layer. The wafer bond alignment mark layer includes an alignment mark at a side of the opening. The cap has a capping portion disposed on the wafer bond alignment mark layer corresponding to the opening.

    Abstract translation: 提供了一种用于晶片接合的可循环印模装置和可循环印模工艺。 可回收印章装置包括基板，保护层，叠层膜结构和盖。 保护层设置在基板上。 开口位于衬底和保护层上以露出衬底。 叠层膜结构包括粘合层，应力控制层和晶片接合对准标记层。 粘合层设置在保护层和暴露的基底上。 应力控制层设置在粘合层上。 晶片接合对准标记层设置在应力控制层上。 晶片接合对准标记层包括在开口侧的对准标记。 盖具有设置在与开口对应的晶片接合对准标记层上的封盖部分。

    Method for forming vias in a substrate
    3.
    发明授权
    Method for forming vias in a substrate 有权
    在基板中形成通孔的方法

    公开(公告)号：US08524602B2

    公开(公告)日：2013-09-03

    申请号：US12876721

    申请日：2010-09-07

    Applicant: Meng-Jen Wang

    Inventor： Meng-Jen Wang

    IPC: H01L21/44

    CPC classification number: H01L21/76898

    Abstract: The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even.

    Abstract translation: 本发明涉及一种在衬底中形成通孔的方法，包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在基板上形成凹槽; （c）用导电金属填充凹槽; （d）去除围绕所述导电金属的所述衬底的一部分，其中所述导电金属被保持以在所述导电金属和所述衬底之间形成容纳空间; （e）在容纳空间中形成绝缘材料; 和（f）去除衬底的第二表面的一部分以暴露导电金属和绝缘材料。 以这种方式，可以在容纳空间中形成更厚的绝缘材料，并且容纳空间中的绝缘材料的厚度是均匀的。

    Package process of stacked type semiconductor device package structure
    6.
    发明授权
    Package process of stacked type semiconductor device package structure 有权
    封装工艺堆叠式半导体器件封装结构

    公开(公告)号：US08338235B2

    公开(公告)日：2012-12-25

    申请号：US12766549

    申请日：2010-04-23

    Applicant: Meng-Jen Wang

    Inventor： Meng-Jen Wang

    IPC: H01L21/00

    CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2224/81 ,  H01L2924/00

    Abstract: A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.

    Abstract translation: 提供包装过程。 封装工艺包括：将半导体衬底设置在载体上，其中半导体衬底在面向载体的一侧具有多个触点; 从半导体衬底的背面稀薄半导体衬底，然后在薄化的半导体衬底中形成多个通过硅通孔; 在所述半导体衬底上形成多个第一焊盘，其中所述第一焊盘分别连接到所述通孔硅通孔; 将多个芯片接合到所述半导体基板，其中所述芯片电连接到相应的焊盘; 在所述半导体衬底上形成模塑料以覆盖所述芯片和所述第一焊盘; 分离半导体衬底和载体，然后在半导体衬底上形成多个焊球; 并锯切模塑料和半导体衬底。

    Semiconductor Device With A Plurality Of Mark Through Substrate Vias
    7.
    发明申请
    Semiconductor Device With A Plurality Of Mark Through Substrate Vias 有权
    具有多个标记的半导体器件通过基板通孔

    公开(公告)号：US20120119335A1

    公开(公告)日：2012-05-17

    申请号：US12945134

    申请日：2010-11-12

    Applicant: Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

    Inventor： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

    IPC: H01L29/41

    CPC classification number: H01L23/544 ,  H01L23/481 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16146

    Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, comprising a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying to the position and direction on the backside surface. Thus, the redistribution layer (RDL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

    Abstract translation: 本发明涉及具有多个标记通过衬底通孔的半导体器件，包括半导体衬底，多个原始通过衬底通孔和多个通过衬底通孔的标记。 原始通过衬底通孔和通过衬底通孔的标记设置在半导体衬底中并从半导体衬底的背面突出。 通过基板通孔的标记在特定位置和/或特定图案中添加，并且用作基准标记，其有助于识别背面上的位置和方向。 因此，再分配层（RDL）或用于实现背侧对准（BSA）的专用设备是不必要的。

    Method for Forming a Via in a Substrate and Substrate with a Via
    8.
    发明申请
    Method for Forming a Via in a Substrate and Substrate with a Via 有权
    用于在基板和基板中形成通孔的方法

    公开(公告)号：US20110189852A1

    公开(公告)日：2011-08-04

    申请号：US13085311

    申请日：2011-04-12

    Applicant: Meng-Jen Wang ,  Chung-Hsi Wu

    Inventor： Meng-Jen Wang ,  Chung-Hsi Wu

    IPC: H01L21/28

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.

    Abstract translation: 本发明涉及一种在衬底中形成通孔的方法，该方法包括以下步骤：（a）提供具有第一表面和第二表面的衬底; （b）在所述基板的第一表面上形成容纳槽和多个柱，所述容纳槽具有侧壁和底壁，所述柱保持在所述容纳槽的底壁上; （c）在容纳槽中和柱之间形成第一绝缘材料; （d）移除所述支柱以在所述第一绝缘材料中形成多个凹槽; 和（e）在槽中形成第一导电金属。 结果，可以在通孔中形成更厚的绝缘材料，并且通孔中的绝缘材料的厚度是均匀的。

    Method for Making a Chip Package
    9.
    发明申请
    Method for Making a Chip Package 有权
    制造芯片封装的方法

    公开(公告)号：US20110159638A1

    公开(公告)日：2011-06-30

    申请号：US12795300

    申请日：2010-06-07

    Applicant: Meng-Jen Wang

    Inventor： Meng-Jen Wang

    IPC: H01L21/56

    CPC classification number: H01L21/561 ,  H01L21/56 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

    Abstract: The present invention relates to a method for making a chip package. The method includes the following steps: (a) providing a substrate having at least one conductive via; (b) disposing the substrate on a carrier; (c) removing part of the substrate, so as to expose the conductive via, and form at least one through via; (d) disposing a plurality of chips on a surface of the substrate, wherein the chips are electrically connected to the through via of the substrate; (e) forming an encapsulation; (f) removing the carrier; (g) conducting a flip-chip mounting process; (h) removing the encapsulation; and (i) forming a protective material. Whereby, the carrier and the encapsulation can avoid warpage of the substrate during the manufacturing process.

    Abstract translation: 本发明涉及一种制造芯片封装的方法。 该方法包括以下步骤：（a）提供具有至少一个导电通孔的基板; （b）将基板设置在载体上; （c）去除所述衬底的一部分，以暴露所述导电通孔，并形成至少一个通孔; （d）在所述基板的表面上设置多个芯片，其中所述芯片与所述基板的贯通孔电连接; （e）形成封装; （f）清除载体; （g）进行倒装芯片安装工艺; （h）去除封装; 和（i）形成保护材料。 由此，载体和封装可以避免在制造过程中基板翘曲。

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