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    Magnetic random access memory and method of fabricating thereof
    1.
    发明授权
    Magnetic random access memory and method of fabricating thereof 有权
    磁性随机存取存储器及其制造方法

    公开(公告)号：US07183130B2

    公开(公告)日：2007-02-27

    申请号：US10604533

    申请日：2003-07-29

    申请人： Joachim Nuetzel ,  Xian Jay Ning ,  William C. Wille

    发明人： Joachim Nuetzel ,  Xian Jay Ning ,  William C. Wille

    IPC分类号： H01L21/66 ,  H01L21/00 ,  H01L21/961

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15

    摘要： A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.

    摘要翻译： 一种用于在磁随机存取存储器（MRAM）装置中形成互连结构的装置结构和方法。 在示例性实施例中，该方法包括在下部金属化层面上限定磁性层叠层，磁性堆叠层包括设置在一对铁磁层之间的非铁磁层。 导电硬掩模被定义在磁性堆叠层上，然后去除硬掩模和磁性堆叠层的选定部分，由此形成磁性隧道结（MTJ）堆叠的阵列。 MTJ堆叠包括磁堆叠层和硬掩模的剩余部分，其中硬掩模在磁堆叠层和随后形成在MTJ叠层之上的上金属化层之间形成自对准接触。

    Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices
    2.
    发明授权
    Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices 有权
    无磁阵列保护工艺流程，用于在磁性随机存取存储器件中形成互连通孔

    公开(公告)号：US06784091B1

    公开(公告)日：2004-08-31

    申请号：US10250133

    申请日：2003-06-05

    申请人： Joachim Nuetzel ,  Christian Arndt ,  Greg Costrini ,  Michael C. Gaidis ,  Xian Jay Ning

    发明人： Joachim Nuetzel ,  Christian Arndt ,  Greg Costrini ,  Michael C. Gaidis ,  Xian Jay Ning

    IPC分类号： H01L2128

    CPC分类号： H01L27/222 ,  B82Y10/00 ,  H01L21/76802 ,  H01L27/228

    摘要： A method for forming interconnect structures in a magnetic random access memory (MRAM) device includes defining an array of magnetic tunnel junction (MTJ) stacks over a lower metallization level. A encapsulating dielectric layer is formed over the array of MTJ stacks and the lower metallization level. Then, a via opening is defined in the encapsulating dielectric layer, and a planar interlevel dielectric (ILD) layer is deposited over the encapsulating dielectric layer and within the via opening. Openings are then formed within ILD layer, over the array of MTJ stacks and the via opening.

    摘要翻译： 用于在磁随机存取存储器（MRAM）器件中形成互连结构的方法包括在较低金属化层级上定义磁隧道结（MTJ）堆叠的阵列。 封装介电层形成在MTJ叠层阵列和下金属化层上。 然后，在密封介电层中限定通孔，并且在封装介电层上方和通孔开口内沉积平面层间电介质（ILD）层。 然后在ILD层内，在MTJ堆叠阵列和通孔开口上形成开口。

    MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THEREOF
    3.
    发明申请
    MAGNETIC RANDOM ACCESS MEMORY AND METHOD OF FABRICATING THEREOF 有权
    磁性随机存取存储器及其制造方法

    公开(公告)号：US20050023581A1

    公开(公告)日：2005-02-03

    申请号：US10604533

    申请日：2003-07-29

    申请人： Joachim Nuetzel ,  Xian Jay Ning ,  William Wille

    发明人： Joachim Nuetzel ,  Xian Jay Ning ,  William Wille

    IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L21/00 ,  H01L29/76 ,  H01L31/062 ,  H01L43/00

    CPC分类号： H01L27/228 ,  B82Y10/00 ,  G11C11/15

    摘要： A device structure and method for forming an interconnect structure in a magnetic random access memory (MRAM) device. In an exemplary embodiment, the method includes defining a magnetic stack layer on a lower metallization level, the magnetic stack layer including a non-ferromagnetic layer disposed between a pair of ferromagnetic layers. A conductive hardmask is defined over the magnetic stack layer, and selected portions of the hardmask and the magnetic stack layer, are then removed, thereby creating an array of magnetic tunnel junction (MTJ) stacks. The MTJ stacks include remaining portions of the magnetic stack layer and the hardmask, wherein the hardmask forms a self aligning contact between the magnetic stack layer and an upper metallization level subsequently formed above the MTJ stacks.

    摘要翻译： 一种用于在磁随机存取存储器（MRAM）装置中形成互连结构的装置结构和方法。 在示例性实施例中，该方法包括在下部金属化层面上限定磁性层叠层，磁性堆叠层包括设置在一对铁磁层之间的非铁磁层。 导电硬掩模被定义在磁性堆叠层上，然后去除硬掩模和磁性堆叠层的选定部分，由此形成磁性隧道结（MTJ）堆叠的阵列。 MTJ堆叠包括磁堆叠层和硬掩模的剩余部分，其中硬掩模在磁堆叠层和随后形成在MTJ叠层之上的上金属化层之间形成自对准接触。

    Transistor, memory cell and method of manufacturing a transistor
    4.
    发明申请
    Transistor, memory cell and method of manufacturing a transistor 审中-公开
    晶体管，存储单元及制造晶体管的方法

    公开(公告)号：US20070176253A1

    公开(公告)日：2007-08-02

    申请号：US11343812

    申请日：2006-01-31

    申请人： Peng-Fei Wang ,  Rolf Weis ,  Joachim Nuetzel ,  Arnd Scholz ,  Alexander Sieck ,  Sigurd Zehner

    发明人： Peng-Fei Wang ,  Rolf Weis ,  Joachim Nuetzel ,  Arnd Scholz ,  Alexander Sieck ,  Sigurd Zehner

    IPC分类号： H01L29/00

    CPC分类号： H01L27/10876 ,  H01L27/10867

    摘要： A transistor which can in particular be used in memory cells of a Dynamic Random Access Memory a memory cell and a method of manufacturing a transistor is disclosed. In one embodiment the transistor is a dual-fin field effect transistor. The transistor includes a first and a second source/drain regions, a channel connecting the first and second source/drain regions, a gate electrode for controlling an electrical current flowing between the first and second source/drain regions. The gate electrode is insulated from the channel by a gate dielectric, wherein the gate electrode is disposed in a gate groove extending in the substrate surface so that the channel comprises two fin-like channel portions extending between the first and second source/drain regions in a cross-sectional view taken perpendicularly to a line connecting the first and the second source/drain regions, the gate electrode delimiting each of the fin-like channel portions at one side thereof.

    摘要翻译： 公开了一种特别可用于动态随机存取存储器存储单元的存储单元的晶体管，以及制造晶体管的方法。 在一个实施例中，晶体管是双鳍场效应晶体管。 晶体管包括第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道，用于控制在第一和第二源极/漏极区域之间流动的电流的栅电极。 栅极通过栅极电介质与沟道绝缘，其中栅电极设置在在衬底表面中延伸的栅极沟槽中，使得沟道包括在第一和第二源极/漏极区之间延伸的两个鳍状沟道部分 垂直于连接第一和第二源极/漏极区域的线截取的截面图，栅极电极在其一侧限定每个鳍状沟道部分。

    Method of forming isolation dummy fill structures
    5.
    发明授权
    Method of forming isolation dummy fill structures 失效
    形成隔离假填充结构的方法

    公开(公告)号：US06913990B2

    公开(公告)日：2005-07-05

    申请号：US10628149

    申请日：2003-07-28

    申请人： Joachim Nuetzel

    发明人： Joachim Nuetzel

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L27/22

    CPC分类号： H01L21/76819

    摘要： A method of providing dummy fill structures to meet the strict requirements for planarizing MRAM (Magnetic Random Access Memory) and other semiconductor devices to gain silicon floor space and allow maximum use of wiring levels. The method deposits a sacrificial or dummy layer of dielectric material such as SiO2 to form dummy fill structures prior to the planarization steps. The insulative dummy fill structures allow the use of less precise lithography and etching methods. The dummy fill structures provide support during the CMP process that planarizes the active devices prior to depositing another layer of SiO2 and etching lines of metallization. Since the dummy structures are made of a dielectric rather than conductive materials, the risk of shorts between levels of metallization and between active devices and lines of metallization is reduced.

    摘要翻译： 一种提供虚拟填充结构以满足对MRAM（磁随机存取存储器）和其他半导体器件进行平坦化的严格要求以获得硅占地面积并允许最大限度地使用布线级别的方法。 该方法在平坦化步骤之前沉积诸如SiO 2的介电材料的牺牲层或虚拟层以形成虚拟填充结构。 绝缘虚拟填充结构允许使用不太精确的光刻和蚀刻方法。 虚拟填充结构在CMP工艺期间提供支撑，其在沉积另一层SiO 2层和蚀刻金属化线之前平坦化有源器件。 由于虚拟结构由电介质而不是导电材料制成，所以金属化水平与有源器件与金属化线之间的短路风险降低。

    Semiconductor memory device with a capacitor formed therein and a method for forming the same
    7.
    发明授权
    Semiconductor memory device with a capacitor formed therein and a method for forming the same 失效
    其中形成有电容器的半导体存储器件及其形成方法

    公开(公告)号：US07341875B2

    公开(公告)日：2008-03-11

    申请号：US10478642

    申请日：2002-05-21

    申请人： Joachim Nuetzel ,  Till Schloesser ,  Siegfried Schwarzl ,  Stefan Wurn

    发明人： Joachim Nuetzel ,  Till Schloesser ,  Siegfried Schwarzl ,  Stefan Wurn

    IPC分类号： H01L21/00

    CPC分类号： H01L27/222 ,  B82Y10/00

    摘要： To integrate a capacitor device (40) into the region of a semiconductor memory device with a particularly small number of process steps, a lower electrode device (43) and an upper electrode device (44) of the capacitor device (40) are provided to be formed directly underneath or directly above the material region (30) which has the memory elements (20), in such a way that as a result at least a part of the material region (30) which has the memory elements (20) functions at least as part of the respective dielectric (45) between the electrodes devices (43, 44).

    摘要翻译： 为了以特别少的工艺步骤将电容器器件（40）集成到半导体存储器件的区域中，电容器器件（40）的下电极器件（43）和上电极器件（44）被提供到 直接在具有存储元件（20）的材料区域（30）的正下方或直接形成，使得至少一部分具有存储元件（20）的材料区域（30）起作用 至少作为电极装置（43,44）之间的相应电介质（45）的一部分。

    MRAM MTJ stack to conductive line alignment method
    8.
    发明授权
    MRAM MTJ stack to conductive line alignment method 失效
    MRAM MTJ堆叠到导线对准方法

    公开(公告)号：US06858441B2

    公开(公告)日：2005-02-22

    申请号：US10234864

    申请日：2002-09-04

    申请人： Joachim Nuetzel ,  Xian J. Ning ,  Kia-Seng Low ,  Gill Yong Lee ,  Rajiv M. Ranade ,  Ravikumar Ramachandran

    发明人： Joachim Nuetzel ,  Xian J. Ning ,  Kia-Seng Low ,  Gill Yong Lee ,  Rajiv M. Ranade ,  Ravikumar Ramachandran

    IPC分类号： H01L23/544 ,  H01L27/22 ,  H01L21/28

    CPC分类号： H01L27/222 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    摘要： A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).

    摘要翻译： 一种制造电阻半导体存储器件（100）的方法，包括在工件（30）上沉积绝缘层（132），并且限定用于多个对准标记（128）和多条导线（112）的图案， 在绝缘层（132）内。 导电材料沉积在晶片上以填充对准标记（128）和导线（112）图案。 绝缘层（132）顶表面被化学机械抛光以从绝缘层（132）去除多余的导电材料并形成导电线（112），同时留下导电材料留在对准标记（128）内。 掩模层（140）形成在导电线（112）之上，并且导电材料的至少一部分从对准标记（128）内移除。 对准标记（128）用于电阻式存储器件（100）的后续沉积层的对准。

    Integrated circuit device and method of manufacture
    9.
    发明授权
    Integrated circuit device and method of manufacture 失效
    集成电路器件及其制造方法

    公开(公告)号：US07763513B2

    公开(公告)日：2010-07-27

    申请号：US11222540

    申请日：2005-09-09

    申请人： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Hannes Luyken

    发明人： Peng-Fei Wang ,  Joachim Nuetzel ,  Rolf Weis ,  Till Schloesser ,  Marc Strasser ,  Hannes Luyken

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66621 ,  H01L21/28114 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of manufacturing a transistor is disclosed. The method includes forming a first and a second source/drain regions, a channel connecting the first and the second source/drain regions and a gate electrode for controlling the conductivity of the channel. The gate electrode is formed by defining a gate groove in the substrate, and defining a pocket in each of the isolation trenches at a position adjacent to the groove so that the two pockets will be connected with the groove and the groove is disposed between the two pockets. A gate insulating material is provided at an interface between the active area and the groove and at an interface between the active area and the pockets. A gate electrode material is deposited so as to fill the groove and the two pockets.

    摘要翻译： 公开了制造晶体管的方法。 该方法包括形成第一和第二源极/漏极区域，连接第一和第二源极/漏极区域的沟道和用于控制沟道的导电性的栅电极。 栅极通过在衬底中限定栅极沟槽并且在与沟槽相邻的位置处在每个隔离沟槽中限定一个凹穴形成，使得两个凹穴将与凹槽连接，凹槽设置在两个凹槽之间 口袋 栅极绝缘材料设置在有源区域和凹槽之间的界面处以及在有源区域和凹穴之间的界面处。 沉积栅电极材料以填充凹槽和两个凹穴。