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    NOR and NAND memory arrangement of resistive memory elements
    2.
    发明授权
    NOR and NAND memory arrangement of resistive memory elements 有权
    NOR和NAND存储器布置的电阻存储器元件

    公开(公告)号：US07746683B2

    公开(公告)日：2010-06-29

    申请号：US11737236

    申请日：2007-04-19

    申请人： Kurt Hoffmann ,  Christine Dehm ,  Recai Sezi ,  Andreas Walter

    发明人： Kurt Hoffmann ,  Christine Dehm ,  Recai Sezi ,  Andreas Walter

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0019 ,  G11C2213/15 ,  G11C2213/75 ,  G11C2213/79

    摘要： A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

    摘要翻译： 存储器装置包括：用于施加参考电压的第一线，用于施加工作电压的第二线和多个电阻性存储器元件，每个元件包括电阻存储器单元和MOS存储单元选择晶体管。 NOR存储器配置配置有每个存储器元件，其包括与连接到第一线路的晶体管串联连接的电阻存储器单元和选择晶体管，以及连接到第二线路的存储器单元。 NAND存储器配置配置有一系列形成链的电阻存储元件，每个存储元件包括并联连接的电阻存储单元和选择晶体管。 链条连接到布置在面向选择晶体管的存储单元的一侧上的第一行，而第二行设置在远离选择晶体管的存储单元的一侧。

    NOR and NAND Memory Arrangement of Resistive Memory Elements
    3.
    发明申请
    NOR and NAND Memory Arrangement of Resistive Memory Elements 有权
    NOR和NAND内存排列的电阻式存储元件

    公开(公告)号：US20070242496A1

    公开(公告)日：2007-10-18

    申请号：US11737236

    申请日：2007-04-19

    申请人： Kurt Hoffmann ,  Christine Dehm ,  Recai Sezi ,  Andreas Walter

    发明人： Kurt Hoffmann ,  Christine Dehm ,  Recai Sezi ,  Andreas Walter

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  B82Y10/00 ,  G11C13/0004 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/0019 ,  G11C2213/15 ,  G11C2213/75 ,  G11C2213/79

    摘要： A memory arrangement includes: a first line for applying a reference voltage, a second line for applying an operating voltage, and a plurality of resistive memory elements, each element includes a resistive memory cell and a MOS memory cell selection transistor. A NOR memory arrangement is configured with each memory element including the resistive memory cell and selection transistor connected in series with the transistor connected to the first line, and the memory cell connected to the second line. A NAND memory arrangement is configured with a series of resistive memory elements forming a chain with each memory element including the resistive memory cell and selection transistor connected in parallel. The chain is connected to the first line disposed on a side of the memory cells facing the selection transistors and the second line disposed on a side of the memory cells which is remote from the selection transistors.

    摘要翻译： 存储器装置包括：用于施加参考电压的第一线，用于施加工作电压的第二线和多个电阻性存储器元件，每个元件包括电阻存储器单元和MOS存储单元选择晶体管。 NOR存储器配置配置有每个存储器元件，其包括与连接到第一线路的晶体管串联连接的电阻存储器单元和选择晶体管，以及连接到第二线路的存储器单元。 NAND存储器配置配置有一系列形成链的电阻存储元件，每个存储元件包括并联连接的电阻存储单元和选择晶体管。 链条连接到布置在面向选择晶体管的存储单元的一侧上的第一行，而第二行设置在远离选择晶体管的存储单元的一侧。

    Semiconductor memory cell and semiconductor memory device
    6.
    发明授权
    Semiconductor memory cell and semiconductor memory device 失效
    半导体存储单元和半导体存储器件

    公开(公告)号：US06787832B2

    公开(公告)日：2004-09-07

    申请号：US10395457

    申请日：2003-03-24

    申请人： Günter Schmid ,  Marcus Halik ,  Hagen Klauk ,  Christine Dehm ,  Thomas Haneder ,  Thomas Mikolajick

    发明人： Günter Schmid ,  Marcus Halik ,  Hagen Klauk ,  Christine Dehm ,  Thomas Haneder ,  Thomas Mikolajick

    IPC分类号： H01L2976

    CPC分类号： B82Y10/00 ,  H01L21/28291 ,  H01L27/1159 ,  H01L29/6684

    摘要： A semiconductor memory cell has a field-effect transistor device and a ferroelectric storage capacitor. The field-effect transistor device has a channel region that includes or is made of an organic semiconductor material. Besides a first gate electrode of the gate electrode configuration of the field-effect transistor device, an additional selection gate electrode is provided, by way of which the field-effect transistor device can be switched off without influencing the storage dielectric and independently of the first gate electrode.

    摘要翻译： 半导体存储单元具有场效晶体管器件和铁电存储电容器。 场效应晶体管器件具有包含或由有机半导体材料制成的沟道区。 除了场效应晶体管器件的栅电极结构的第一栅电极之外，还提供附加的选择栅电极，通过该栅电极可以切断场效晶体管器件而不影响存储电介质，并且独立于第一栅电极 栅电极。

    Titanium polycide stabilization with a porous barrier
    7.
    发明授权
    Titanium polycide stabilization with a porous barrier 失效
    具有多孔屏障的多晶硅化钛稳定剂

    公开(公告)号：US6057220A

    公开(公告)日：2000-05-02

    申请号：US936029

    申请日：1997-09-23

    申请人： Atul C. Ajmera ,  Christine Dehm ,  Anthony G. Domenicucci ,  George G. Gifford ,  Stephen K. Loh ,  Christopher Parks ,  Viraj Y. Sardesai

    发明人： Atul C. Ajmera ,  Christine Dehm ,  Anthony G. Domenicucci ,  George G. Gifford ,  Stephen K. Loh ,  Christopher Parks ,  Viraj Y. Sardesai

    IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L21/44 ,  H01L21/425

    CPC分类号： H01L21/28061 ,  H01L29/4933

    摘要： A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.

    摘要翻译： 通过用氮富集多晶硅体的晶界而形成不形成离散阻挡层的“多孔阻挡层”，以抑制硅物质的热迁移率。 在多晶硅栅极/互连结构中，硅的迁移率降低抑制了在其上形成的金属硅化物层中的硅的聚集。 由于硅团聚是多杀线反转现象的前体，因此有效地避免了可能刺穿潜在氧化物并导致器件故障的多硅化物反转。 因此，多晶硅结构和包括多晶硅体在内的其他结构的热稳定性增加，因此增加了可被该结构承受的热量预算，并且增加了存在多晶硅所产生的制造工艺窗口，这可以在其它工艺中被利用，例如退火 开发包括在多晶硅结构中的难熔金属硅化物的低电阻相，用于形成场效应晶体管的源极/漏极区域的驱动退火等。

    Semiconductor storage component with storage cells, logic areas and filling structures
    10.
    发明授权
    Semiconductor storage component with storage cells, logic areas and filling structures 有权
    具有存储单元，逻辑区域和填充结构的半导体存储组件

    公开(公告)号：US06670662B1

    公开(公告)日：2003-12-30

    申请号：US09980386

    申请日：2002-03-19

    申请人： Christine Dehm ,  Guenther Schindler

    发明人： Christine Dehm ,  Guenther Schindler

    IPC分类号： H01L27108

    CPC分类号： H01L27/10844 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/60

    摘要： The invention provides a semiconductor memory component with random access, also having a structure which is differentiated into memory cells and logic regions and has a lower oxide layer arranged on a silicon substrate and an upper oxide layer arranged on the lower oxide layer, each memory cell comprising at least one transistor in the transition region between silicon substrate and lower oxide layer and a capacitor in the transition region between lower oxide layer and upper oxide layer, which capacitor is connected to the transistor via a contact hole, which is filled with metal, in the lower oxide layer and comprises a ferroelectric arranged between two electrodes, the electrode which is connected to the transistor and adjoins the lower oxide layer having a relatively great thickness, and each logic region comprising at least one transistor in the transition region between silicon substrate and lower oxide layer, which transistor is connected to an electrode on the topside of the upper oxide layer via a contact hole, which is filled with metal, in the lower oxide layer and the upper oxide layer. According to the invention, it is provided that between the capacitors of the memory cells and the contact holes in the logic regions, level compensation between the topology of the memory cells and of the logic regions is created by dummy structures.

    摘要翻译： 本发明提供了具有随机存取的半导体存储器组件，其还具有分为存储单元和逻辑区域的结构，并且具有布置在硅衬底上的低氧化物层和布置在低氧化物层上的上氧化层，每个存储单元 包括在硅衬底和低氧化物层之间的过渡区域中的至少一个晶体管和在低氧化物层和上部氧化物层之间的过渡区域中的电容器，该电容器通过填充有金属的接触孔连接到晶体管， 在所述低氧化物层中并且包括布置在两个电极之间的铁电体，所述电极连接到所述晶体管并且邻接所述低氧化物层具有相对较大的厚度，并且每个逻辑区域包括在硅衬底之间的过渡区域中的至少一个晶体管 和低氧化物层，该晶体管连接到u的顶部上的电极 通过在低氧化物层和上部氧化物层中填充有金属的接触孔来形成氧化皮层。 根据本发明，提供在存储单元的电容器和逻辑区域中的接触孔之间，通过虚拟结构产生存储器单元的拓扑和逻辑区域之间的电平补偿。