公开(公告)号：US08703620B2

公开(公告)日：2014-04-22

申请号：US13564071

申请日：2012-08-01

申请人： Joanna Wasyluk ,  Stephan Kronholz ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

发明人： Joanna Wasyluk ,  Stephan Kronholz ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

IPC分类号： H01L21/302

CPC分类号： H01L21/02057 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878

摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

摘要翻译： 一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。 第一部分和第二部分通过浅沟槽隔离特征电隔离。 该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。 提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。 该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

公开(公告)号：US20130203245A1

公开(公告)日：2013-08-08

申请号：US13564071

申请日：2012-08-01

申请人： Joanna WASYLUK ,  Stephan KRONHOLZ ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

发明人： Joanna WASYLUK ,  Stephan KRONHOLZ ,  Berthold Reimer ,  Sven Metzger ,  Gregory Nowling ,  John Foster ,  Paul Besser

IPC分类号： H01L21/20

CPC分类号： H01L21/02057 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/76232 ,  H01L21/823807 ,  H01L21/823878

摘要： A method for fabricating an integrated circuit from a semiconductor substrate having formed thereon over a first portion of the semiconductor substrate a hard mask layer and having formed thereon over a second portion of the semiconductor substrate an oxide layer. The first portion and the second portion are electrically isolated by a shallow trench isolation feature. The method includes removing the oxide layer from over the second portion and recessing the surface region of the second portion by applying an ammonia-hydrogen peroxide-water (APM) solution to form a recessed surface region. The APM solution is provided in a concentration of ammonium to hydrogen peroxide ranging from about 1:1 to about 1:0.001 and in a concentration of ammonium to water ranging from about 1:1 to about 1:20. The method further includes epitaxially growing a silicon-germanium (SiGe) layer on the recessed surface region.

摘要翻译： 一种用于从半导体衬底制造集成电路的方法，其中半导体衬底的第一部分上形成有硬掩模层，并且在半导体衬底的第二部分上形成氧化物层。 第一部分和第二部分由浅沟槽隔离特征电隔离。 该方法包括通过施加氨 - 过氧化氢 - 水（APM）溶液以形成凹入的表面区域，从第二部分上方去除氧化物层并使第二部分的表面区域凹陷。 提供APM溶液的浓度为约1：1至约1：0.001的过氧化氢，铵浓度为约1：1至约1:20的水。 该方法还包括在凹表面区域上外延生长硅 - 锗（SiGe）层。

公开(公告)号：US20060267107A1

公开(公告)日：2006-11-30

申请号：US11252493

申请日：2005-10-17

申请人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

发明人： Robert Chiu ,  Jeffrey Patton ,  Paul Besser ,  Minh Ngo

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/28518

摘要： A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform suicides are formed on the source/drain junctions, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the ultra-uniform silicides.

摘要翻译： 提供集成电路的结构。 在半导体衬底上形成栅极电介质，并且在半导体衬底上的栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极结上形成超均匀的硅化物，并且在半导体衬底上沉积电介质层。 然后在电介质层中形成与超均匀硅化物的接触。

公开(公告)号：US20050085073A1

公开(公告)日：2005-04-21

申请号：US10687186

申请日：2003-10-16

申请人： Sergey Lopatin ,  Paul Besser ,  Alline Myers ,  Jeremias Romero ,  Minh Tran ,  Lu You ,  Connie Wang

发明人： Sergey Lopatin ,  Paul Besser ,  Alline Myers ,  Jeremias Romero ,  Minh Tran ,  Lu You ,  Connie Wang

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/76877

摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

摘要翻译： 示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。 该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。 粘附前体层由气体形成，电介质材料包括孔。

公开(公告)号：US06461951B1

公开(公告)日：2002-10-08

申请号：US09280662

申请日：1999-03-29

申请人： Paul Besser ,  Angela Hui ,  Yowjuang W. Liu

发明人： Paul Besser ,  Angela Hui ,  Yowjuang W. Liu

IPC分类号： H01L213205

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6656

摘要： A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.

摘要翻译： 用于形成凹陷间隔物以防止在接触蚀刻或局部互连蚀刻工艺期间器件结的气蚀在形成栅极侧壁上的侧壁间隔物期间故意破坏间隔物材料层的方法和装置。 然后，在硅化过程中形成的硅化物覆盖栅极侧壁的暴露部分。 在栅极侧壁上形成硅化物防止在局部互连蚀刻或接触蚀刻期间侧壁间隔物被优先攻击。

公开(公告)号：US06365516B1

公开(公告)日：2002-04-02

申请号：US09483081

申请日：2000-01-14

申请人： Austin Frenkel ,  Akif Sultan ,  Paul Besser

发明人： Austin Frenkel ,  Akif Sultan ,  Paul Besser

IPC分类号： H01L2144

CPC分类号： H01L21/0206 ,  H01L21/28518

摘要： Various methods of fabricating a silicide structure are provided. In one aspect, a method of fabricating a circuit structure on a silicon surface is provided that includes exposing the silicon surface to a plasma ambient containing hydrogen and an inert gas, and depositing a metallic material capable of forming silicide on the silicon surface. The metallic material is heated to form a metal silicide on the silicon surface. The method provides for low sheet resistance silicide structures by eliminating native oxide films without the risk of spacer material backsputtering.

摘要翻译： 提供了制造硅化物结构的各种方法。 一方面，提供一种在硅表面上制造电路结构的方法，其包括将硅表面暴露于含有氢气和惰性气体的等离子体环境中，以及在硅表面上沉积能够形成硅化物的金属材料。 金属材料被加热以在硅表面上形成金属硅化物。 该方法通过消除天然氧化物膜而不会产生间隔材料反溅镀的风险，从而提供低电阻硅化物结构。

公开(公告)号：US06258697B1

公开(公告)日：2001-07-10

申请号：US09502333

申请日：2000-02-11

申请人： Jayendra Bhakta ,  Paul Besser ,  Minh Van Ngo

发明人： Jayendra Bhakta ,  Paul Besser ,  Minh Van Ngo

IPC分类号： H01L2176

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76224

摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrate. Oxide is deposited as a trench liner in the trench using low pressure chemical vapor deposition (LPCVD) high temperature oxidation (HTO). As LPCVD is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overetch at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

摘要翻译： 半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。 使用低压化学气相沉积（LPCVD）高温氧化（HTO）将氧化物作为沟槽衬垫沉积在沟槽中。 由于LPCVD是应力中性过程，因此避免了硅衬底和氧化物层之间的界面中的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处过蚀刻。 当局部互连形成时，这减少了结漏电的可能性。

公开(公告)号：US08723321B2

公开(公告)日：2014-05-13

申请号：US11448788

申请日：2006-06-08

申请人： Christy Woo ,  Jun “Charlie” Zhai ,  Paul Besser ,  Kok-Yong Yiang ,  Richard C. Blish ,  Christine Hau-Riege

发明人： Christy Woo ,  Jun “Charlie” Zhai ,  Paul Besser ,  Kok-Yong Yiang ,  Richard C. Blish ,  Christine Hau-Riege

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

摘要翻译： 通过图案化之后Cu线和其上的覆盖层之间的剥离应力通过改变通孔的形状并定位通孔来减小，以增加通孔和线边缘之间的空间，从而增加电迁移寿命。 实施例包括改变通孔的形状，如通过形成椭圆形或矩形形状的通孔，使得椭圆形的短轴与线之间的比例或矩形的宽度与线宽的比率小于 约0.7。

公开(公告)号：US06333218B1

公开(公告)日：2001-12-25

申请号：US09501995

申请日：2000-02-11

申请人： Minh Van Ngo ,  Jayendra Bhakta ,  Paul Besser

发明人： Minh Van Ngo ,  Jayendra Bhakta ,  Paul Besser

IPC分类号： H01L218238

CPC分类号： H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/31612 ,  H01L21/76224

摘要： A method for manufacturing a semiconductor device forms a trench of a trench isolation region in a portion of a top surface of a semiconductor substrates. Oxide is deposited as a trench liner in the trench using high temperature high density plasma (HDP) deposition. As the high temperature HDP oxide deposition is a stress neutral process, stress defects in an interface between the silicon substrate and the oxide layer are avoided, so that subsequent etching steps in a local interconnect process are less likely to overreach at the interface. This reduces the possibility of junction leakage when the local interconnect is formed.

摘要翻译： 半导体器件的制造方法在半导体衬底的顶表面的一部分中形成沟槽隔离区的沟槽。 使用高温高密度等离子体（HDP）沉积，氧化物作为沟槽衬垫沉积在沟槽中。 由于高温HDP氧化物沉积是应力中性过程，因此避免了硅衬底和氧化物层之间的界面处的应力缺陷，使得局部互连工艺中的后续蚀刻步骤不太可能在界面处超范围。 当局部互连形成时，这减少了结漏电的可能性。

公开(公告)号：US20080286921A1

公开(公告)日：2008-11-20

申请号：US11748743

申请日：2007-05-15

申请人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

发明人： Wen Yu ,  Paul Besser ,  Bin Yang ,  Haijiang Yu ,  Simon S. Chan

IPC分类号： H01L21/8234

CPC分类号： H01L21/324 ,  H01L21/28052 ,  H01L29/66507 ,  H01L29/78

摘要： The gate and active regions of a device are formed and alternating steps of applying and removing nitride and oxide layers allows exposing silicon in different areas while keeping silicon or polysilicon in other area covered with nitride. Metal layers are deposited over the exposed silicon or polysilicon and annealing forms a silicide layer in the selected exposed areas. The oxide and/or nitride layers are removed from the covered areas and another metal layer is deposited. The anneal process is repeated with silicide of one thickness formed over the second exposed areas with additional thickness of silicide formed over the previous silicide thickness.

摘要翻译： 形成器件的栅极和有源区，并且施加和去除氮化物和氧化物层的交替步骤允许在不同区域暴露硅，同时保持覆盖有氮化物的其它区域中的硅或多晶硅。 金属层沉积在暴露的硅或多晶硅上，退火在所选择的暴露区域中形成硅化物层。 氧化物层和/或氮化物层从被覆盖区域移除，另一个金属层被沉积​​。 在第二暴露区域上形成一层厚度的硅化物，并在先前的硅化物厚度上形成附加的硅化物厚度来重复退火工艺。