利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

68 条记录 (耗时 0.023 秒)

    Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers
    1.
    发明授权
    Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers 有权
    形成侧壁间隔物的方法，以防止包括在栅极间隔物上的硅化物生长的层间电介质蚀刻期间器件结的气蚀

    公开(公告)号：US06461951B1

    公开(公告)日：2002-10-08

    申请号：US09280662

    申请日：1999-03-29

    申请人： Paul Besser ,  Angela Hui ,  Yowjuang W. Liu

    发明人： Paul Besser ,  Angela Hui ,  Yowjuang W. Liu

    IPC分类号： H01L213205

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L29/665 ,  H01L29/6656

    摘要： A method and arrangement for forming a recessed spacer to prevent the gouging of device junctions during a contact etch or local interconnect etch process deliberately overetches the spacer material layer during the formation of sidewall spacers on the sidewalls of a gate. The exposed portions of the gate sidewalls are then covered by silicide formed during a silicidation process. The formation of the suicide on the gate sidewalls prevents the sidewall spacers from being preferentially attacked during a local interconnect etch or contact etch.

    摘要翻译： 用于形成凹陷间隔物以防止在接触蚀刻或局部互连蚀刻工艺期间器件结的气蚀在形成栅极侧壁上的侧壁间隔物期间故意破坏间隔物材料层的方法和装置。 然后，在硅化过程中形成的硅化物覆盖栅极侧壁的暴露部分。 在栅极侧壁上形成硅化物防止在局部互连蚀刻或接触蚀刻期间侧壁间隔物被优先攻击。

    Method to improve LDD corner control with an in-situ film for local interconnect processing
    2.
    发明授权
    Method to improve LDD corner control with an in-situ film for local interconnect processing 失效
    用于局部互连处理的用于改善LDD角部控制的方法

    公开(公告)号：US06483153B1

    公开(公告)日：2002-11-19

    申请号：US09418316

    申请日：1999-10-14

    申请人： Angela Hui ,  Paul Besser ,  Minh-Van Ngo

    发明人： Angela Hui ,  Paul Besser ,  Minh-Van Ngo

    IPC分类号： H01L2976

    CPC分类号： H01L21/76897 ,  H01L21/76895

    摘要： A method to improve LDD corner control during a local interconnect trench oxide etch on a semiconductor device by providing a first etch stop layer over the gate and active regions in the substrate and further providing thereon a second etch stop layer made of polysilicon and having of a different composition than that of the first etch stop layer. By forming a second etch stop layer of polysilicon the present invention improves the selectivity of the local interconnect trench oxide etch, thereby improving the ability of the first and second etch stop layers to stop the etch process at the critical interfaces.

    摘要翻译： 一种在半导体器件上的局部互连沟槽氧化物蚀刻期间，通过在衬底上的栅极和有源区上提供第一蚀刻停止层并且还在其上提供由多晶硅制成的第二蚀刻停止层来改善LDD拐角控制的方法， 不同于第一蚀刻停止层的组成。 通过形成多晶硅的第二蚀刻停止层，本发明改善了局部互连沟槽氧化物蚀刻的选择性，从而提高了第一和第二蚀刻停止层在关键界面处停止蚀刻工艺的能力。

    SI trench between bitline HDP for BVDSS improvement
    5.
    发明授权
    SI trench between bitline HDP for BVDSS improvement 有权
    位线HDP之间的SI沟槽改善BVDSS

    公开(公告)号：US07951675B2

    公开(公告)日：2011-05-31

    申请号：US11957737

    申请日：2007-12-17

    申请人： Lei Xue ,  Aimin Xing ,  Chih-Yuh Yang ,  Angela Hui ,  Chungho Lee

    发明人： Lei Xue ,  Aimin Xing ,  Chih-Yuh Yang ,  Angela Hui ,  Chungho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/76224 ,  H01L27/10885

    摘要： Memory devices having improved BVdss characteristics and methods of making the memory devices are provided. The memory devices contain bitline dielectrics on bitlines of a semiconductor substrate; first spacers adjacent the side surfaces of the bitline dielectrics and on the upper surface of the semiconductor substrate; a trench in the semiconductor substrate between the first spacers; and second spacers adjacent the side surfaces of the trench. By containing the trench and the first and second spacers between the bitlines, the memory device can improve the electrical isolation between the bitlines, thereby preventing and/or mitigating bitline-to-bitline current leakage and increasing BVdss.

    摘要翻译： 提供了具有改进的BVdss特性的存储器件和制造存储器件的方法。 存储器件在半导体衬底的位线上包含位线电介质; 邻近所述位线电介质的侧表面并在所述半导体衬底的上表面上的第一间隔物; 在所述第一间隔物之间​​的所述半导体衬底中的沟槽; 以及邻近沟槽的侧表面的第二间隔件。 通过在位线之间容纳沟槽和第一和第二间隔物，存储器件可以改善位线之间的电隔离，从而防止和/或减轻位线到位线的电流泄漏并增加BVdss。

    Selective contact formation using masking and resist patterning techniques
    6.
    发明授权
    Selective contact formation using masking and resist patterning techniques 有权
    使用掩模和抗蚀剂图案化技术的选择性接触形成

    公开(公告)号：US07622389B1

    公开(公告)日：2009-11-24

    申请号：US11411353

    申请日：2006-04-25

    申请人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    发明人： Kyunghoon Min ,  Mark Chang ,  Ning Cheng ,  Brian Osborn ,  Kevin Song ,  Fei Wang ,  Angela Hui ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang

    IPC分类号： H01L21/302

    CPC分类号： H01L27/11526 ,  H01L27/11548

    摘要： A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.

    摘要翻译： 包括选择性导电触点的半导体器件的制造方法包括在第一和第二存储器件部件上沉积抗蚀剂的步骤，第一和第二部件中的每一个包括形成在衬底中的接合部以及在接合部之间形成在衬底上的栅极。 然后将抗蚀剂从第二部件移除，从而在每个第二部件控制浇口和结上形成抗蚀剂开口。 然后蚀刻抗蚀剂，从而暴露第一组分控制栅极中的每一个，而不暴露围绕第一组分控制栅极的衬底。 然后在暴露的第一部件控制栅极和第二部件控制栅极和结上形成导电触点。

    Method for fabricating a memory device having reverse LDD
    10.
    发明授权
    Method for fabricating a memory device having reverse LDD 有权
    用于制造具有反向LDD的存储器件的方法

    公开(公告)号：US06936515B1

    公开(公告)日：2005-08-30

    申请号：US10387774

    申请日：2003-03-12

    申请人： Hiroyuki Ogawa ,  Yu Sun ,  Angela Hui

    发明人： Hiroyuki Ogawa ,  Yu Sun ,  Angela Hui

    IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/105

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66825

    摘要： A method for fabricating a semiconductor device. Specifically, a method that includes forming a source and drain region in a periphery transistor, exhibiting a channel width between the source and drain regions suitable for operation at predetermined voltages. After forming the source and drain regions, to eliminate diffusion of lightly doped drain regions resulting from a later formation of the source and drain regions, forming the lightly doped drain regions adjacent to the source and drain regions of the periphery transistor. After forming the lightly doped drain regions in the periphery transistor, the method includes forming a source region and a drain region in a core memory cell, independent of forming the source and drain regions in the periphery transistor.

    摘要翻译： 一种半导体器件的制造方法。 具体地，涉及在周边晶体管中形成源区和漏区的方法，其表现出适于在预定电压下操作的源区和漏区之间的沟道宽度。 在形成源极区和漏极区之后，为了消除稍后形成源极和漏极区所产生的轻掺杂漏极区的扩散，形成与周边晶体管的源极和漏极区相邻的轻掺杂漏极区。 在周边晶体管中形成轻掺杂的漏极区之后，该方法包括在核心存储单元中形成源极区和漏极区，与形成周边晶体管中的源极和漏极区无关。