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10 条记录 (耗时 0.144 秒)

    Fast check bit write for a semiconductor memory
    1.
    发明授权
    Fast check bit write for a semiconductor memory 失效
    快速检查位写入半导体存储器

    公开(公告)号：US5638385A

    公开(公告)日：1997-06-10

    申请号：US785625

    申请日：1991-10-31

    申请人： John A. Fifield ,  Duane E. Galbi ,  Hsing-San Lee

    发明人： John A. Fifield ,  Duane E. Galbi ,  Hsing-San Lee

    IPC分类号： G06F11/10 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42

    CPC分类号： G06F11/1008 ,  G06F11/1076

    摘要： A memory device having an on-chip ECC system includes an array of memory cells, some of which have wider transistors than others so that they have faster access speeds. Data bits are written into ordinary memory cells and the check bits are written into the faster cells in order to make up for the delay associated with the calculation of the check bits.

    摘要翻译： 具有片上ECC系统的存储器件包括一组存储器单元，其中一些具有比其他晶体管更宽的晶体管，使得它们具有更快的存取速度。 数据位被写入普通存储器单元，并将校验位写入更快的单元，以补偿与计数校验位有关的延迟。

    Shadow ram cell having a shallow trench eeprom
    3.
    发明授权
    Shadow ram cell having a shallow trench eeprom 失效
    阴影柱塞细胞具有浅沟eeprom

    公开(公告)号：US5196722A

    公开(公告)日：1993-03-23

    申请号：US848913

    申请日：1992-03-12

    申请人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    发明人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/788

    CPC分类号： H01L27/10829 ,  H01L27/105 ,  H01L29/7881

    摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

    摘要翻译： 公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。 浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。 本发明的阵列提供高密度影子RAM。 还公开了用于制造本发明的装置的方法。

    Accessing arrangement for memories with small cells
    4.
    发明授权
    Accessing arrangement for memories with small cells 失效
    使用小电池存储器的安装

    公开(公告)号：US4160275A

    公开(公告)日：1979-07-03

    申请号：US892605

    申请日：1978-04-03

    申请人： Hsing-San Lee ,  Wilbur D. Pricer ,  Norbert G. Vogl, Jr.

    发明人： Hsing-San Lee ,  Wilbur D. Pricer ,  Norbert G. Vogl, Jr.

    IPC分类号： G11C11/401 ,  G11C11/35 ,  G11C11/4097 ,  G11C11/24 ,  G11C7/06

    CPC分类号： G11C11/35 ,  G11C11/4097

    摘要： A merged charge memory system is provided having an accessing arrangement wherein each of the word lines of the memory array is divided into a plurality of segments with cells associated only with a selected one or a portion of the segments being coupled at any particular time to bit driving and sensing means. Thus, only relatively few sense amplifiers compared with the number of bits per word of the array are required to handle all of the cells of the array. More particularly, in the merged charge memory system of the present invention, the flow of charges from charge source means is released only to the cells of the selected word segment or segments which are simultaneously coupled to bit driving and sensing means via associated bit/sense lines.

    摘要翻译： 合并的电荷存储器系统具有访问布置。 存储器阵列的每个字线被分成多个段，其中单元仅与选定的一个或一部分段相关联，在任何特定时间被耦合到位驱动和感测设备。 因此，仅需要相对较少的读出放大器与阵列的每个字的位数相比较来处理阵列的所有单元。 来自电荷源的电荷流仅释放到所选择的字段的单元或通过相关联/感测线同时耦合到位驱动和感测装置的段。 -

    Sense amplifier control circuit
    6.
    发明授权
    Sense amplifier control circuit 失效
    感应放大器控制电路

    公开(公告)号：US4825410A

    公开(公告)日：1989-04-25

    申请号：US112348

    申请日：1987-10-26

    申请人： Hsing-San Lee

    发明人： Hsing-San Lee

    IPC分类号： G11C11/41 ,  G11C7/06 ,  G11C11/419 ,  G11C13/00

    CPC分类号： G11C7/06

    摘要： An improved memory sensing control circuit is provided wherein pulses derived from row or word address changes and from column or bit address changes are used to produce set pulses which are applied at optimum time intervals to a sense amplifier. More particularly, the memory sensing control circuit includes first and second paths for transmitting a bit decoder drive pulse coupled to a sense amplifier set device and means responsive to pulses derived from row or word and column or bit address change detecting means for selecting one of the first and second paths.

    Twin nodes capacitance memory
    7.
    发明授权
    Twin nodes capacitance memory 失效
    双电源电容存储器

    公开(公告)号：US4040016A

    公开(公告)日：1977-08-02

    申请号：US672196

    申请日：1976-03-31

    申请人： Hsing-San Lee ,  Norbert George Vogl, Jr.

    发明人： Hsing-San Lee ,  Norbert George Vogl, Jr.

    IPC分类号： G11C11/405 ,  G11C11/24 ,  G11C11/35 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40

    CPC分类号： H01L27/108 ,  G11C11/24 ,  G11C11/35

    摘要： A semiconductor memory produced in a unipolar technology includes a cell which has a pair of inversion capacitors with one terminal of each capacitor connected to one of a pair of bit/sense lines, the other terminal of each capacitor is coupled to a source of charges by a pulse from a word line. The charges produced from the source may be in the form of pulses injected into the capacitors. To provide a word organized array of these cells, each word includes a source of charges produced at the surface of a semiconductor substrate and a plurality of pairs of inversion capacitors formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the pairs of capacitors by applying complementary voltages to each pair of bit/sense lines coupled to the pairs of capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The complementary voltages have a first and a second magnitude. When voltages of the first and second magnitudes are applied to first and second bit/sense lines, respectively, of a pair of bit/sense lines, a 1 bit of information is stored in the associated cell, and when voltages of the second and first magnitudes are applied to the first and second bit/sense lines, respectively, of the same pair of bit/sense lines, a 0 bit of information is stored in the associated cell. The capacitor of the pair of capacitors having the larger voltage applied thereto stores the greater amount of charge. By employing a differential sense amplifier and floating the pair of bit sense line when a word pulse again connects the charge source with each of the capacitors, the greater charge can be detected by noting the polarity of the different voltage between the two capacitors of the pair of capacitors.

    Sensing technique for memories with small cells
    9.
    发明授权
    Sensing technique for memories with small cells 失效
    用小细胞记忆的感应技术

    公开(公告)号：US4301519A

    公开(公告)日：1981-11-17

    申请号：US145927

    申请日：1980-05-02

    申请人： Hsing-San Lee

    发明人： Hsing-San Lee

    IPC分类号： G11C7/06 ,  G11C11/34 ,  G11C11/35 ,  G11C11/40

    CPC分类号： G11C11/35 ,  G11C7/065

    摘要： A sensing technique or system is provided for a merged charge memory having similar storage and dummy cells with the dummy cells being charged with a reference voltage equal to 1/2 of the sum of the voltages representing 1 and 0 binary digits of information in the memory. The sensing technique or system includes an insulating layer disposed on a semiconductor substrate, a memory array having a data word line coupled to a first plurality of spaced apart conductive films formed on the insulating layer defining a plurality of data storage capacitors, sensing means having first and second terminals and a dummy line coupled to a second plurality of spaced apart conductive films formed on the insulating layer defining a plurality of reference voltage capacitors. Charge source means are coupled to the first plurality of conductive films by the word line and to the second plurality of conductive films by the dummy line. The first terminal of the sensing means is coupled to a conductive film of the first plurality of films spaced a predetermined distance from the charge source means and the second terminal of the sensing means is coupled to a given conductive film of the second plurality of films spaced the predetermined distance from the charge source means. The reference voltage is derived from the first and second terminals of the sensing means and applied to the given conductive film.

    摘要翻译： 为具有类似存储和虚拟单元的合并电荷存储器提供感测技术或系统，其中虚设单元被充电等于表示存储器中信息的1和0二进制数字的电压之和的1/2的参考电压 。 感测技术或系统包括设置在半导体衬底上的绝缘层，存储器阵列，其具有耦合到限定多个数据存储电容器的绝缘层上形成的第一多个间隔开的导电膜的数据字线，感测装置具有第一 以及第二端子和耦合到形成在限定多个参考电压电容器的绝缘层上的第二多个间隔开的导电膜的虚拟线。 电荷源装置通过字线耦合到第一多个导电膜，并通过虚拟线耦合到第二多个导电膜。 感测装置的第一端子耦合到与电荷源装置隔开预定距离的第一多个膜的导电膜，并且感测装置的第二端子耦合到第二多个膜的给定导电膜间隔开 距离电荷源装置的预定距离。 参考电压从感测装置的第一和第二端子导出并施加给给定的导电膜。

    Injected charge capacitor memory
    10.
    发明授权
    Injected charge capacitor memory 失效
    注射电容器存储器

    公开(公告)号：US4040017A

    公开(公告)日：1977-08-02

    申请号：US672198

    申请日：1976-03-31

    申请人： Hsing-San Lee

    发明人： Hsing-San Lee

    IPC分类号： G11C11/56 ,  G11C11/35 ,  G11C11/403 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H04N3/14 ,  H01L27/14

    CPC分类号： G11C11/35 ,  G11C11/403 ,  H01L27/108

    摘要： A semiconductor memory produced in a unipolar technology includes a cell which has an inversion capacitor with one terminal connected to a bit/sense line, the other terminal is coupled to a source of charges by a pulse from a word line. The charges are produced from the source in the form of pulses injected into the capacitor. To provide a word organized array of these cells, each word includes a source of pulsed charges produced at the surface of a semiconductor substrate and a plurality of inversion capacitors are formed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the pulsed charge source with each of the capacitors. The pulses of charge are timed so that they begin at least by the onset of the word pulse and terminate prior to the termination of the word pulse. Furthermore, prior to the termination of the word pulse, the voltage at the charge source is set to form a charge sink for draining excess charges. The capacitors having the larger voltage applied to the one terminal of the capacitors store the greater amount of charge. This charge can then be detected by measuring the voltage of the floating bit sense line when a word pulse again connects the charge source with each of the capacitors.