公开(公告)号：US20080111938A1

公开(公告)日：2008-05-15

申请号：US11972735

申请日：2008-01-11

Applicant: Jong-Dae PARK ,  Seok-Won LEE ,  Tae-Jin LEE

Inventor： Jong-Dae PARK ,  Seok-Won LEE ,  Tae-Jin LEE

IPC: G02F1/1333 ,  G09G3/36

CPC classification number: G02F1/133308 ,  G02F2001/133311 ,  G02F2001/133317 ,  G02F2201/465

Abstract: A supporting unit includes a first support frame, a second support frame and an impurity barrier. The first support frame supports an LCD panel, and includes an opening through which a light is supplied to the LCD panel. The second support frame is protruded from sides of the first support frame to surround sides of the LCD panel. The impurity barrier is disposed on a surface of the first support frame corresponding to the liquid crystal display panel to prevent an inflow of impurities into a space between the first support frame and the liquid crystal display panel. Therefore, the supporting unit for the LCD panel includes the impurity barrier to prevent the inflow of the impurities that is externally provided into the space between the supporting unit and the LCD panel, thereby improving image display quality.

Abstract translation: 支撑单元包括第一支撑框架，第二支撑框架和杂质屏障。 第一支撑框架支撑LCD面板，并且包括一个开口，通过该开口将光提供给LCD面板。 第二支撑框架从第一支撑框架的侧面突出以围绕LCD面板的侧面。 杂质阻挡层设置在与液晶显示面板对应的第一支撑框架的表面上，以防止杂质流入第一支撑框架和液晶显示面板之间的空间。 因此，用于LCD面板的支撑单元包括杂质阻挡层，以防止外部设置在支撑单元和LCD面板之间的空间中的杂质的流入，从而提高图像显示质量。

公开(公告)号：US20170200736A1

公开(公告)日：2017-07-13

申请号：US15349084

申请日：2016-11-11

Applicant: Jinwoo PARK ,  Jaeshin PARK ,  Joyoung PARK ,  Jiwoong SUE ,  Seok-Won LEE

Inventor： Jinwoo PARK ,  Jaeshin PARK ,  Joyoung PARK ,  Jiwoong SUE ,  Seok-Won LEE

IPC: H01L27/115 ,  H01L21/768 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/11582 ,  H01L21/76879 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L29/0649

Abstract: A semiconductor memory device includes a substrate that includes a first cell array region and a peripheral region, a plurality of stack structures that extend in the first direction on the first cell array region and are spaced apart from each other in a second direction crossing the first direction, an insulation layer that covers the stack structures, and at least one separation structure that extends in the second direction on the peripheral region and penetrates the insulation layer in a direction normal to a top surface of the substrate.

公开(公告)号：US20150137216A1

公开(公告)日：2015-05-21

申请号：US14534181

申请日：2014-11-06

Applicant: Seok-Won LEE ,  Joon-Hee LEE ,  Dong-Seog EUN ,  Chang-Hyun LEE

Inventor： Seok-Won LEE ,  Joon-Hee LEE ,  Dong-Seog EUN ,  Chang-Hyun LEE

IPC: H01L27/115 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

Abstract translation: 垂直存储器件包括衬底，通道，栅极线和连接部分。 多个通道在与基板的顶表面垂直的第一方向上延伸。 多个栅极线在第一方向上被堆叠以彼此间隔开并且在第二长度方向上延伸，每个栅极线与通道组的每组通道的每个通道的外侧壁相交。 栅极线形成包括多个垂直电平的阶梯结构。 连接部分连接位于相同垂直高度的多条栅极线的一组栅极线，该连接部分从栅极线组的栅极线延伸的第二方向发散。

公开(公告)号：US20120007165A1

公开(公告)日：2012-01-12

申请号：US13181281

申请日：2011-07-12

Applicant: Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

Inventor： Myoung-Bum LEE ,  Jae-Hwang SIM ,  In-Sun PARK ,  Jin-Gi HONG ,  Ju-Seon GOO ,  Seung-Bae PARK ,  Seung-Yup LEE ,  Du-Heon SONG ,  Jeong-Dong CHOE ,  Seok-Won LEE

IPC: H01L29/788 ,  H01L27/088

CPC classification number: H01L29/7881 ,  H01L21/764 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, a first insulating interlayer pattern, and a second insulation layer pattern. The substrate has an active region and a field region, each of the active region and the field region extends in a first direction, and the active region and the field region are alternately and repeatedly arranged in a second direction substantially perpendicular to the first direction. The gate structures are spaced apart from each other in the first direction, each of the gate structures extends in the second direction. The first insulation layer pattern is formed on a portion of a sidewall of each gate structure. The second insulation layer pattern covers the gate structures and the first insulation layer pattern, and has an air tunnel between the gate structures, the air tunnel extending in the second direction.

Abstract translation: 半导体器件包括衬底，多个栅极结构，第一绝缘层间图案和第二绝缘层图案。 基板具有有源区域和场区域，有源区域和场区域中的每一个沿着第一方向延伸，并且有源区域和场区域在基本上垂直于第一方向的第二方向上交替地和重复地布置。 栅极结构在第一方向上彼此间隔开，每个栅极结构沿第二方向延伸。 第一绝缘层图案形成在每个栅极结构的侧壁的一部分上。 第二绝缘层图案覆盖栅极结构和第一绝缘层图案，并且在栅极结构之间具有沿第二方向延伸的空气通道的空气通道。

公开(公告)号：US20080081456A1

公开(公告)日：2008-04-03

申请号：US11941421

申请日：2007-11-16

Applicant: Dong-Han KIM ,  Sa-Yoon KANG ,  Seok-Won LEE

Inventor： Dong-Han KIM ,  Sa-Yoon KANG ,  Seok-Won LEE

IPC: H01L21/44

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/90 ,  H01L2224/11334 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/189 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: A chip-on-board (COB) package has a flip chip assembly structure and is used for an integrated circuit (IC) card. The COB package has conductive patterns as contact terminals on an outer surface of a non-conductive film, and an IC chip on an inner surface of the film. The film has a number of holes through which the conductive patterns are partly exposed. A number of conductive bumps on an active surface of the IC chip face the inner surface of the film and enter corresponding holes in the non-conductive film to mechanically join and electrically couple to the conductive patterns. The disclosed COB package and a related manufacturing method allow a reduction in production cost, simplified process, better electrical connections, and improved reliability.

Abstract translation: 片上芯片（COB）封装具有倒装芯片组装结构，用于集成电路（IC）卡。 COB封装具有作为非导电膜的外表面上的接触端子的导电图案和膜的内表面上的IC芯片。 该膜具有多个孔，导电图案通过该孔部分露出。 IC芯片的有源表面上的多个导电凸块面向薄膜的内表面，并且在非导电薄膜中进入相应的孔以机械地连接并电耦合到导电图案。 所公开的COB封装和相关制造方法允许降低生产成本，简化工艺，更好的电连接和改进的可靠性。