公开(公告)号：US20050092348A1

公开(公告)日：2005-05-05

申请号：US10701708

申请日：2003-11-05

申请人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Ju-Chien Chiang ,  Ming-Huan Tsai ,  Huan-Just Lin ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： B08B3/08 ,  B08B3/12 ,  C11D3/39 ,  C11D7/08 ,  C11D11/00 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L21/02052 ,  B08B3/08 ,  B08B3/12 ,  C11D3/3947 ,  C11D7/08 ,  C11D11/0047 ,  H01L21/31122

摘要： The present invention provides aqueous compositions for cleaning integrated circuit substrates. Specifically, in the cleaning of an integrated circuit substrate, disclosed is a method for removing the by-products of the high-k dielectric dry etch process from the integrated circuit substrate, the method including: contacting the integrated circuit substrate with an aqueous composition including an amount, effective for the purpose of a (a) hydrogen fluoride, followed by (b) a mixture of hydrogen peroxide with a compound selected from the group consisting of ammonium hydroxide, hydrochloric acid and sulfuric acid.

摘要翻译： 本发明提供用于清洁集成电路基板的水性组合物。 具体地，在集成电路基板的清洗中，公开了从集成电路基板除去高介电常数干蚀刻工艺的副产物的方法，该方法包括：使集成电路基板与水性组合物接触，所述水性组合物包括 （a）氟化氢，其次是（b）过氧化氢与选自氢氧化铵，盐酸和硫酸的化合物的混合物的量。

公开(公告)号：US06828205B2

公开(公告)日：2004-12-07

申请号：US10072798

申请日：2002-02-07

申请人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ming-Jie Huang ,  Huan-Just Lin ,  Hun-Jan Tao

IPC分类号： H01L218222

CPC分类号： H01L21/31111 ,  H01L21/28123 ,  H01L21/32139

摘要： A method for using an isotropic wet etching process chemical process for trimming semiconductor feature sizes with improved critical dimension control including providing a hard mask overlying a substrate included in a semiconductor wafer said hard mask patterned for masking a portion of the substrate for forming a semiconductor feature according to an anisotropic plasma etching process; isotropically wet etching the hard mask to reduce a dimension of the hard mask prior to carrying out the anisotropic plasma etching process; and, anisotropically plasma etching a portion of the substrate not covered by the hard mask to form the semiconductor feature.

摘要翻译： 一种使用各向同性湿蚀刻工艺化学工艺的方法，用于修整具有改进的临界尺寸控制的半导体特征尺寸，包括提供覆盖在半导体晶片中的衬底的硬掩模，所述硬掩模被图案化以掩蔽用于形成半导体特征的衬底的一部分 根据各向异性等离子体蚀刻工艺; 在进行各向异性等离子体蚀刻工艺之前，均匀地湿式蚀刻硬掩模以减小硬掩模的尺寸; 并且各向异性等离子体蚀刻未被硬掩模覆盖的衬底的一部分以形成半导体特征。

公开(公告)号：US20050081781A1

公开(公告)日：2005-04-21

申请号：US10688045

申请日：2003-10-17

申请人： Huan-Just Lin ,  Ming-Huan Tsai ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Huan-Just Lin ,  Ming-Huan Tsai ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14 ,  H01L21/28 ,  H01L21/311 ,  H01L21/316 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31645 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513

摘要： A fully dry etch method is described for removing a high k dielectric layer from a substrate without damaging the substrate and has a high selectivity with respect to a gate layer. The etch is comprised of BCl3, a fluorocarbon, and an inert gas. A low RF bias power is preferred. The method can also be used to remove an interfacial layer between the substrate and the high k dielectric layer. A HfO2 etch rate of 55 Angstroms per minute is achieved without causing a recess in a silicon substrate and with an etch selectivity to polysilicon of greater than 10:1. Better STI oxide divot control is also provided by this method. The etch through the high k dielectric layer may be performed in the same etch chamber as the etch process to form a gate electrode.

摘要翻译： 描述了用于从衬底去除高k电介质层而不损坏衬底并且相对于栅极层具有高选择性的全干蚀刻方法。 蚀刻由BCl 3 3，碳氟化合物和惰性气体组成。 低RF偏置功率是优选的。 该方法也可以用于去除衬底和高k电介质层之间的界面层。 实现了每分钟55埃的HfO 2/2蚀刻速率，而不会在硅衬底中产生凹陷，并且对多晶硅的蚀刻选择性大于10:1。 该方法也提供更好的STI氧化物控制。 通过高k介电层的蚀刻可以在与蚀刻工艺相同的蚀刻室中进行以形成栅电极。

公开(公告)号：US20050127459A1

公开(公告)日：2005-06-16

申请号：US11048205

申请日：2005-02-01

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L21/2652 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

摘要翻译： 描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。 首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。 然后将高k电介质材料衬垫沉积在所有暴露的表面上。 然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。 然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。 在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件 硅衬底。

公开(公告)号：US06867084B1

公开(公告)日：2005-03-15

申请号：US10263541

申请日：2002-10-03

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Fang-Cheng Chen ,  Hun-Jan Tao

IPC分类号： H01L21/265 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/80

CPC分类号： H01L21/2652 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A field effect transistor gate structure and a method of fabricating the gate structure with a high-k gate dielectric material and high-k spacer are described. A gate pattern or trench is first etched in a dummy organic or inorganic film deposited over a silicon substrate with source/drain regions. A high-k dielectric material liner is then deposited on all exposed surfaces. Excess poly-silicon gate conductor film is then deposited within and over the trench to provide adequate overburden. Poly-silicon is then planarized with chemical mechanical polishing or etch-back methods such that the high-k material film on top of the dummy film surface is removed during this step. In the final step, the dummy film is disposed off, leaving the final transistor gate structure with high-k gate dielectric and high-k spacer surrounding the gate conductor poly-silicon, with the entire gate structure fabricated to form an FET device on a silicon substrate.

摘要翻译： 描述了场效应晶体管栅极结构和制造具有高k栅极介电材料和高k隔离物的栅极结构的方法。 首先在具有源极/漏极区域的硅衬底上沉积的虚拟有机或无机膜中蚀刻栅极图案或沟槽。 然后将高k电介质材料衬垫沉积在所有暴露的表面上。 然后将过多的多晶硅栅极导体膜沉积在沟槽内和沟槽上，以提供足够的覆盖层。 然后通过化学机械抛光或蚀刻方法对多晶硅进行平面化，使得在该步骤期间去除虚拟膜表面顶部的高k材料膜。 在最后的步骤中，将虚设薄膜放开，留下最终的晶体管栅极结构，其中高k栅极电介质和围绕栅极导体多晶硅的高k隔离层，整个栅极结构被制成以形成FET器件 硅衬底。

公开(公告)号：US07078351B2

公开(公告)日：2006-07-18

申请号：US10361875

申请日：2003-02-10

申请人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Jeng-Horng Chen

发明人： Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Jeng-Horng Chen

IPC分类号： H01L21/302

CPC分类号： H01L21/0276 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76802

摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.

摘要翻译： 首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。 然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。 根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。 然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。 衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。 从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

公开(公告)号：US06407002B1

公开(公告)日：2002-06-18

申请号：US09636583

申请日：2000-08-10

申请人： Li-Te Lin ,  Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao

发明人： Li-Te Lin ,  Yuan-Hung Chiu ,  Ming-Huan Tsai ,  Hun-Jan Tao

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  H01L21/31138 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76877

摘要： A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.

摘要翻译： 提供了一种提高半导体衬底中的开孔的钨，W填充的方法。 这可以通过形成开口来实现，该开口可以作为接触或通孔使用，与开口的入口以及锥形侧壁一起使用。 面形入口和锥形侧壁的这种组合基本上改善了衬底中的接触/通孔的钨W填充，而没有形成键孔，从而导致高电气完整性和高可靠性的金属插头。

公开(公告)号：US06706640B1

公开(公告)日：2004-03-16

申请号：US10292355

申请日：2002-11-12

申请人： Ming-Huan Tsai ,  Ju-Wang Hsu ,  Peng-Fu Hsu ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ju-Wang Hsu ,  Peng-Fu Hsu ,  Hun-Jan Tao

IPC分类号： H01L21302

CPC分类号： H01L21/28518 ,  H01L21/31116 ,  H01L21/76802

摘要： A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier gas such as argon or helium, but without an oxygen containing gas or a carbon and oxygen containing gas. The plasma etch method is selective for the etch stop layer with respect to the metal silicide layer, thus maintaining the physical and electrical integrity of the metal silicide layer.

摘要翻译： 用于蚀刻介电层和蚀刻停止层以达到其下形成的金属硅化物层的等离子体蚀刻方法用于蚀刻蚀刻停止层包括含氟气体和含氮气体的蚀刻剂气体组合物，优选地使用载气如 作为氩或氦，但不含含氧气体或含碳和氧的气体。 等离子体蚀刻方法对于蚀刻停止层相对于金属硅化物层是选择性的，从而保持金属硅化物层的物理和电气完整性。

公开(公告)号：US06410424B1

公开(公告)日：2002-06-25

申请号：US09837599

申请日：2001-04-19

申请人： Ming-Huan Tsai ,  Chung-Long Chang ,  Chii-Ming Wu ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Chung-Long Chang ,  Chii-Ming Wu ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76804 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76829 ,  H01L21/76831 ,  Y10S438/975

摘要： A new processing sequence is provided for the creation of openings in layers of dielectric. Over a semiconductor surface are successively deposited an etch stop layer, a layer of dielectric and a hard mask layer. An opening is etched in the hard mask layer, the main opening is etched through the layer of dielectric and the etch stop layer. The surface is wet cleaned, after which a thin layer of silicon oxide is CVD deposited over the inside surfaces of the created opening. This thin layer of CVD oxide is subjected to argon sputter, providing of the critical dimensions of the upper region of the opening. Then the process continues with the deposition of the barrier metal, the filling of the opening with a conducting material to create the metal plug and the polishing of the surface of the deposited conducting material.

摘要翻译： 提供了一种新的处理顺序，用于在电介质层中产生开口。 在半导体表面上依次沉积蚀刻停止层，电介质层和硬掩模层。 在硬掩模层中蚀刻开口，通过电介质层和蚀刻停止层蚀刻主开口。 表面被湿清洗，之后在所产生的开口的内表面上CVD沉积薄层的氧化硅。 对CVD氧化物薄层进行氩溅射，提供开口上部区域的临界尺寸。 然后，该过程继续阻挡金属的沉积，用导电材料填充开口以产生金属塞和抛光沉积的导电材料的表面。

公开(公告)号：US20060086690A1

公开(公告)日：2006-04-27

申请号：US10971265

申请日：2004-10-21

申请人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Fong-Yuh Yen ,  Hun-Jan Tao

IPC分类号： C23F1/00 ,  C03C25/68 ,  B44C1/22

CPC分类号： H01L21/31116

摘要： A method of dry etching a dielectric layer is provided that prevents or significantly reduces deep ultraviolet photoresist damage and bird's beak problems. The dry etch method provided comprises the steps of providing a substrate having a dielectric layer overlying at least a portion of the substrate's surface; applying a deep ultraviolet (DUV) photoresist mask having a pattern of exposed area on at least a portion of the dielectric layer; and etching the masked dielectric layer with a plasma formed from a mixture of gases comprising a gaseous fluorine species, hydrogen, and helium.

摘要翻译： 提供了干蚀刻电介质层的方法，其防止或显着降低深紫外光致抗蚀剂损伤和鸟嘴问题。 所提供的干蚀刻方法包括以下步骤：提供具有覆盖在基底表面的至少一部分上的介电层的基底; 在所述电介质层的至少一部分上施加具有暴露区域图案的深紫外（DUV）光致抗蚀剂掩模; 并用由包含气态氟物质，氢气和氦气的气体混合物形成的等离子体蚀刻掩蔽的电介质层。