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公开(公告)号：US06629215B2
公开(公告)日：2003-09-30
申请号：US09811916
申请日：2001-03-19
IPC分类号： G06F1200
CPC分类号： G06F9/30141 , G11C7/1006 , G11C7/1012 , G11C7/22 , G11C2207/229 , Y10S707/99953 , Y10S707/99954
摘要： In order to provide an improved wiring management approach, a multiple port memory apparatus (200) is proposed, which comprises a first memory field of a first memory array (201) of at least three memory arrays (201, 202, 203) storing first data, wherein the first memory field is identified by a first address, a first memory field of a second memory array (202) of the at least three memory arrays (201, 202, 203) storing second data, wherein the first memory field of the second memory array (202) is also identified by the first address, and a first memory field of a third memory array (203) of the at least three memory arrays (201, 202, 203) storing select data indicating, whether the first data or the second data, each stored under the first address but in different memory arrays, have been lastly written.
摘要翻译： 为了提供改进的布线管理方法，提出了一种多端口存储装置（200），其包括至少存储有第一存储器阵列（201,202,203）的第一存储器阵列（201）的第一存储器阵列（201,202,203） 数据，其中第一存储器字段由第一地址识别，存储第二数据的至少三个存储器阵列（201,202,203）的第二存储器阵列（202）的第一存储器字段，其中第一存储器字段 所述第二存储器阵列（202）也由所述第一地址标识，并且所述至少三个存储器阵列（201,202,203）中的第三存储器阵列（203）的第一存储器字段存储选择数据，所述选择数据指示所述第一存储器阵列 最后写入数据或第二数据，每个存储在第一地址但不同的存储器阵列中。
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公开(公告)号：US5467037A
公开(公告)日：1995-11-14
申请号：US342967
申请日：1994-11-21
CPC分类号： H03K3/356008
摘要： A self resetting CMOS (SRCMOS) circuit operates with a variable clock cycle. Circuit oscillation is avoided in either long or short clock cycles. At the same time, the circuit eliminates overlapping currents by incorporating a ground interrupt device. The reset generation path is optimized to provide a fast and narrow reset pulse. In addition, the circuit saves power.
摘要翻译： 自复位CMOS（SRCMOS）电路以可变的时钟周期工作。 在长或短时钟周期内避免电路振荡。 同时，该电路通过并入接地中断装置来消除重叠电流。 复位产生路径被优化以提供快速和窄的复位脉冲。 此外，电路节省电力。
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3.发明授权公开(公告)号：US07466607B2
公开(公告)日：2008-12-16
申请号：US10955609
申请日：2004-09-30
IPC分类号： G06F13/372 , G06F13/368
CPC分类号： G11C7/22 , G06F13/1689 , G11C7/1072 , G11C7/222 , G11C2207/2272 , G11C2207/2281 , G11C2207/229
摘要： A de-coupled memory access system including a memory access control circuit is configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.
摘要翻译： 包括存储器访问控制电路的去耦合存储器存取系统被配置为产生第一和第二独立的去耦合时间基准。 存储器访问控制电路包括响应于第一时间基准的读取启动电路和用于产生读取使能信号的读取信号，以及响应于第二时间基准的写入启动电路和用于产生独立于第 读使能信号，用于提供对存储器阵列的独立的去耦合的写访问。
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公开(公告)号：US07440312B2
公开(公告)日：2008-10-21
申请号：US11541752
申请日：2006-10-02
CPC分类号： G11C29/50 , G11C7/02 , G11C7/04 , G11C7/1078 , G11C7/1096 , G11C7/14 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C11/41 , G11C29/028 , G11C29/24 , G11C29/50012
摘要： A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.
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5.发明授权Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity 失效具有共享缓存和数据输入/输出电路的多处理器系统，用于传输数据量大于系统总线容量
公开(公告)号：US5581734A
公开(公告)日：1996-12-03
申请号：US101144
申请日：1993-08-02
IPC分类号： G06F12/08 , G06F15/167
CPC分类号： G06F12/0879 , G06F12/084 , G06F12/0855 , G06F12/0851
摘要： A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cache of the present invention uses the additional performance optimization techniques of pipelining cache operations (loads and stores) and burst-mode data accesses. By including built-in pipeline stages, the cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. With regard to the burst-mode data accesses, the widest possible data out of the cache can be stored to, and retrieved from, the cache by one cache access operation. One portion of the data is held in logic in the cache (on the chip), while another portion (corresponding to the system bus width) gets transferred to the requesting element (processor or memory) in one cycle. The held portion of the data can then be transferred in the following machine cycle.
摘要翻译： 提供高性能共享缓存以支持多处理器系统，并允许处理器访问缓存的最大并行性，在每个机器周期中服务一个处理器请求，减少系统响应时间并提高系统吞吐量。 本发明的共享缓存使用流水线高速缓存操作（加载和存储）和突发模式数据访问的附加性能优化技术。 通过包括内置的流水线阶段，缓存可以从每个机器周期从任何处理元素服务一个请求。 这有助于减少系统响应时间以及吞吐量。 关于突发模式数据访问，可以通过一次高速缓存访问操作将高速缓存中的尽可能多的数据存储到高速缓冲存储器中并从高速缓存中检索出来。 数据的一部分保存在高速缓存（芯片上）的逻辑中，而另一部分（对应于系统总线宽度）在一个周期内被传送到请求元件（处理器或存储器）。 然后可以在以下机器周期中传送保存的数据部分。
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公开(公告)号：US20080084780A1
公开(公告)日：2008-04-10
申请号：US11541752
申请日：2006-10-02
CPC分类号： G11C29/50 , G11C7/02 , G11C7/04 , G11C7/1078 , G11C7/1096 , G11C7/14 , G11C7/22 , G11C11/4076 , G11C11/4096 , G11C11/41 , G11C29/028 , G11C29/24 , G11C29/50012
摘要： A memory write timing system includes a modified memory bitcell including a storage device and a write/read circuit for writing/reading data to/from the storage device; and an output circuit for detecting the current state of the storage device.
摘要翻译： 存储器写入定时系统包括：修改的存储器位单元，包括存储装置和用于向存储装置写入/读取数据的写/读电路; 以及用于检测存储装置的当前状态的输出电路。
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7.发明授权System for controlling access to external cache memories of differing size 失效用于控制访问不同大小的外部高速缓冲存储器的系统公开(公告)号：US06604173B1
公开(公告)日：2003-08-05
申请号：US08560227
申请日：1995-11-21
IPC分类号： G06F1204
CPC分类号： G06F12/0886 , G06F12/0802 , G06F2212/601
摘要： A method for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, the method includes determining a smallest cache memory size for use in the at least one external cache memory, and configuring a tag array of the at least one external cache memory to support the smallest determined cache memory size. A system for controlling access to at least one external cache memory in a processing system, the at least one external cache memory having a number of lines of data and a number of bytes per line of data, includes a circuit for configuring each tag field of a plurality of tag fields in a tag array in the at least one external cache memory to have a number of bits sufficient to support a smallest determined cache memory, and utilizing each tag field to determine whether data being accessed resides in the at least one external cache memory.
摘要翻译： 一种用于控制对处理系统中的至少一个外部高速缓冲存储器的访问的方法，所述至少一个外部高速缓冲存储器具有数据行数和每行数据的字节数，所述方法包括确定最小高速缓存存储器大小 用于至少一个外部高速缓冲存储器，以及配置所述至少一个外部高速缓冲存储器的标签阵列以支持最小确定的高速缓存存储器大小。 一种用于控制对处理系统中的至少一个外部高速缓存存储器的访问的系统，所述至少一个外部高速缓冲存储器具有数据行数和每行数据的字节数，包括用于配置每个标签字段的电路 所述至少一个外部高速缓冲存储器中的标签阵列中的多个标签字段具有足以支持最小确定的高速缓存存储器的数量的位，并且利用每个标签字段来确定被访问的数据是否驻留在所述至少一个外部 高速缓存存储器。
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公开(公告)号：US06353558B1
公开(公告)日：2002-03-05
申请号：US09750254
申请日：2000-12-28
IPC分类号： G11C700
CPC分类号： G11C7/1096 , G11C7/1006 , G11C15/00 , G11C15/04
摘要： An apparatus embodiment of the present invention includes a memory array with lines of memory cells. The lines are coupled to respective wordlines. The lines may be selected by a wordline signal that is asserted responsive to a first clock signal being asserted. The apparatus also includes “write wordline” generators coupled to respective ones of the wordlines. A write wordline generator will assert a write wordline signal responsive to a second clock signal being asserted and before the next time the first clock signal is asserted, but after the first clock signal is deasserted. The apparatus further includes a comparator, which has a first set of inputs coupled to bit lines of the memory cells for reading the contents of the cells, and a second set of inputs for reading a data value. The comparator has a compare match output upon which it asserts a compare match signal if the contents matches the data value. In response to the compare match and write wordline signals, a write operation occurs for the line. Due to the timing of the write wordline signal, the write operation advantageously occurs in the same clock cycle during which the line was selected without any additional decoding.
摘要翻译： 本发明的装置实施例包括具有存储单元线的存储器阵列。 这些线连接到相应的字线。 可以通过响应于被断言的第一时钟信号断言的字线信号来选择线。 该装置还包括耦合到相应字线的“写入字线”发生器。 写入字线发生器将响应于被断言的第二时钟信号以及在下一次第一时钟信号被断言之前，但在第一时钟信号被无效之后，断言写入字线信号。 该装置还包括比较器，其具有耦合到存储器单元的位线的第一组输入，用于读取单元的内容，以及用于读取数据值的第二组输入。 比较器具有比较匹配输出，如果内容与数据值匹配，则比较匹配输出。 响应于比较匹配和写入字线信号，对该行进行写入操作。 由于写入字线信号的定时，写入操作有利地在相同的时钟周期中进行，在该时钟周期期间，线被选择而没有任何附加解码。
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9.发明授权Method and apparatus for synchronized pipeline data access of a memory system 失效用于存储器系统的同步流水线数据访问的方法和装置
公开(公告)号：US5615168A
公开(公告)日：1997-03-25
申请号：US538085
申请日：1995-10-02
申请人： George M. Lattimore , Michael K. Ciraula , Manoj Kumar , Joseph M. Poplawski, Jr. , Dieter F. Wendel , Friedrich Wernicke
发明人： George M. Lattimore , Michael K. Ciraula , Manoj Kumar , Joseph M. Poplawski, Jr. , Dieter F. Wendel , Friedrich Wernicke
CPC分类号： G11C7/1072
摘要： A method and apparatus for providing single clock cycle pipelined access of a memory system, which combines synchronization and self resetting techniques, includes an array of memory cells that are arranged into columns and rows and intercoupled by bit lines and word lines. The memory system also includes an address decoder and a sense enable circuit. The address decoder, upon receiving an address, interprets the address to enable a particular word line, or word lines, and to disable precharging of a bit line, or bit lines. With the word line active, the sense enable circuit generates a sense enable signal when the clock signal has encountered a transitional edge, or is in an active state. When the sense enable signal is active, the sense amplifier reads the data from the addressed memory cell via the bit lines to produce output data.
摘要翻译： 用于提供组合同步和自复位技术的存储器系统的单时钟周期流水线访问的方法和装置包括排列成列和行并由位线和字线相互配合的存储器单元阵列。 存储器系统还包括地址解码器和感测使能电路。 地址解码器在接收到地址后，解释地址以启用特定字线或字线，并禁止位线或位线的预充电。 当字线有效时，当时钟信号遇到过渡沿或处于活动状态时，感测使能电路产生检测使能信号。 当感测使能信号有效时，读出放大器通过位线从寻址的存储单元读取数据，以产生输出数据。
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