公开(公告)号：US20110193165A1

公开(公告)日：2011-08-11

申请号：US13088531

申请日：2011-04-18

申请人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

发明人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

摘要翻译： 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US07948008B2

公开(公告)日：2011-05-24

申请号：US11925573

申请日：2007-10-26

申请人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

发明人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

摘要翻译： 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US20090108292A1

公开(公告)日：2009-04-30

申请号：US11925573

申请日：2007-10-26

申请人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

发明人： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

摘要翻译： 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US08395214B2

公开(公告)日：2013-03-12

申请号：US13088531

申请日：2011-04-18

申请人： Jun Liu ,  Di Li ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch

发明人： Jun Liu ,  Di Li ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L23/02

CPC分类号： H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

摘要翻译： 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US08686487B2

公开(公告)日：2014-04-01

申请号：US11763335

申请日：2007-06-14

申请人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

发明人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

摘要： Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

摘要翻译： 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US20080308858A1

公开(公告)日：2008-12-18

申请号：US11763335

申请日：2007-06-14

申请人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

发明人： Gurtej Sandhu ,  Chandra Mouli ,  Di Li

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

摘要： Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

摘要翻译： 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US20070228450A1

公开(公告)日：2007-10-04

申请号：US11277823

申请日：2006-03-29

申请人： Di Li ,  Chandra Mouli

发明人： Di Li ,  Chandra Mouli

IPC分类号： H01L29/788 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： Disclosed is a flash memory device with an enlarged control gate structure, and various methods of make same. In one illustrative embodiment, the device includes a plurality of floating gate structures formed above a semiconducting substrate, an isolation structure positioned between each of the plurality of floating gate structures and a control gate structure comprising a plurality of enlarged end portions, each of the enlarged end portions being positioned between adjacent floating gate structures.

摘要翻译： 公开了一种具有扩大的控制栅极结构的闪速存储器件，以及各种制造方法。 在一个说明性实施例中，该器件包括形成在半导体衬底之上的多个浮动栅极结构，位于多个浮动栅极结构中的每一个之间的隔离结构和包括多个扩大端部的控制栅极结构， 端部位于相邻的浮栅结构之间。

公开(公告)号：US08723235B2

公开(公告)日：2014-05-13

申请号：US13400442

申请日：2012-02-20

申请人： Chandra Mouli

发明人： Chandra Mouli

IPC分类号： H01L29/812

CPC分类号： H01L29/1608 ,  H01L27/098 ,  H01L29/267 ,  H01L29/66848 ,  H01L29/66916 ,  H01L29/808 ,  H01L29/812 ,  Y10S257/90 ,  Y10S257/902 ,  Y10S257/903

摘要： Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.

摘要翻译： 提供了提供具有改进的操作特性的JFET晶体管的器件和方法。 具体地，本发明的一个或多个实施例涉及具有较高二极管导通电压的JFET晶体管。 例如，一个或多个实施例包括具有掺杂碳化硅栅极的JFET，而其他实施例包括具有金属栅极的JFET。 一个或多个实施例还涉及其中可以使用改进的JFET的系统和装置，以及制造改进的JFET的方法。

公开(公告)号：US08481372B2

公开(公告)日：2013-07-09

申请号：US12333012

申请日：2008-12-11

申请人： Chandra Mouli

发明人： Chandra Mouli

IPC分类号： H01L21/337

CPC分类号： H01L27/098 ,  H01L21/22 ,  H01L21/225 ,  H01L21/2251 ,  H01L21/3226 ,  H01L21/385 ,  H01L27/108 ,  H01L27/1203 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/80 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8086

摘要： In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

摘要翻译： 根据本技术，提供了一种JFET器件结构及其制造方法。 具体地，提供了包括具有源极和漏极的半导体衬底的晶体管。 晶体管还包括形成在源极和漏极之间的半导体衬底中的掺杂沟道，该沟道被配置为在源极和漏极之间传导电流。 此外，晶体管具有包括在沟道上形成的半导体材料的栅极和栅极每侧上的电介质间隔物。 源极和漏极在空间上与栅极分离，使得栅极不在漏极和源极之上。

公开(公告)号：US20130140631A1

公开(公告)日：2013-06-06

申请号：US13310145

申请日：2011-12-02

申请人： Kamal Karda ,  Chandra Mouli

发明人： Kamal Karda ,  Chandra Mouli

IPC分类号： H01L29/78 ,  H01L21/762 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L21/76224 ,  H01L21/76232 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

摘要： A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage among adjacent vertical semiconductor devices are described.