利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.021 秒)

    Memory error detection circuitry
    1.
    发明授权
    Memory error detection circuitry 有权
    内存错误检测电路

    公开(公告)号：US08612814B1

    公开(公告)日：2013-12-17

    申请号：US12814713

    申请日：2010-06-14

    申请人： Jun Pin Tan ,  Kiun Kiet Jong ,  Boon Jin Ang

    发明人： Jun Pin Tan ,  Kiun Kiet Jong ,  Boon Jin Ang

    IPC分类号： G01R31/28

    CPC分类号： G11C29/44 ,  G11C11/41 ,  G11C29/40 ,  G11C29/52 ,  G11C2029/0409

    摘要： Integrated circuits with error detection circuitry are provided. Integrated circuits may include memory cells organized into frames. The error detection circuitry may compress each frame to scan for soft errors. The error detection circuitry may include multiple input shift registers (MISRs), a data register, and a signature comparator. The data frames may be read, compressed, and shifted into the MISRs in parallel. After all the data frames have been read, the MISRs may provide a scanned MISR signature at their outputs. Computer-aided design (CAD) tools may be used to calculate a precomputed MISR signature. The precomputed MISR signature may be loaded into the data register. The signature comparator compares the scanned MISR signature with the precomputed MISR signature. If the signatures match, then the device is free of soft errors. If the signatures do not match, then at least one soft error exists.

    摘要翻译： 提供了具有错误检测电路的集成电路。 集成电路可以包括被组织成帧的存储器单元。 错误检测电路可以压缩每个帧以扫描软错误。 错误检测电路可以包括多个输入移位寄存器（MISR），数据寄存器和签名比较器。 数据帧可以被并行读取，压缩和移入MISR中。 在读取所有数据帧之后，MISR可以在其输出端提供扫描的MISR签名。 计算机辅助设计（CAD）工具可用于计算预计算的MISR签名。 预计算的MISR签名可以加载到数据寄存器中。 签名比较器将扫描的MISR签名与预先计算的MISR签名进行比较。 如果签名匹配，则设备没有软错误。 如果签名不匹配，则至少存在一个软错误。

    Integrated circuit with improved interconnect routing and associated methods
    2.
    发明授权
    Integrated circuit with improved interconnect routing and associated methods 有权
    具有改进的互连路由和相关方法的集成电路

    公开(公告)号：US08629689B1

    公开(公告)日：2014-01-14

    申请号：US13475927

    申请日：2012-05-18

    申请人： Jun Pin Tan ,  Kiun Kiet Jong

    发明人： Jun Pin Tan ,  Kiun Kiet Jong

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17736 ,  G06F17/5054 ,  G06F17/5077 ,  H03K19/17776 ,  H03K23/005

    摘要： An integrated circuit (IC) includes a circuit, an encoder, and a decoder. The circuit is coupled to circuitry in the IC via a first set of interconnect fabricated using a metal layer. The encoder encodes a plurality of address lines to provide a plurality of encoded address lines. The decoder decodes the plurality of address lines. The plurality of encoded address lines are routed using a second set of interconnect fabricated using the metal layer.

    摘要翻译： 集成电路（IC）包括电路，编码器和解码器。 电路通过使用金属层制造的第一组互连件耦合到IC中的电路。 编码器对多个地址线进行编码以提供多个编码的地址线。 解码器解码多个地址线。 使用使用金属层制造的第二组互连来路由多个编码地址线。

    Zeroization verification of integrated circuit
    3.
    发明授权
    Zeroization verification of integrated circuit 有权
    集成电路的归零验证

    公开(公告)号：US08437200B1

    公开(公告)日：2013-05-07

    申请号：US13022144

    申请日：2011-02-07

    申请人： Jun Pin Tan ,  Kiun Kiet Jong

    发明人： Jun Pin Tan ,  Kiun Kiet Jong

    IPC分类号： G11C7/06

    CPC分类号： H03K19/17764 ,  G11C7/20 ,  H03K19/17768

    摘要： Methods and circuits for zeroization verification of the memory in an integrated circuit (IC) are provided. One method includes sequentially reading frames from a block of the memory, and sequentially performing a logical operation between each of the frames and the content of a signature register. The result of the logical operation is stored back in the signature register. In another operation, a hardware logical comparison is made between a device hardwired signature block and the content of the signature register, after the logical operations for all the frames have been performed. The device hardwired signature block is a hardware implemented constant that is unavailable for loading in registers of the IC. The block of the memory is verified to hold a fixed value when the result of the hardware logical comparison indicates that the device hardwired signature block is equal to the content of the signature register.

    摘要翻译： 提供了用于集成电路（IC）中的存储器的零位验证的方法和电路。 一种方法包括从存储器的块中顺序读取帧，并且顺序地执行每个帧和签名寄存器的内容之间的逻辑运算。 逻辑运算的结果存储在签名寄存器中。 在另一操作中，在执行了所有帧的逻辑操作之后，在设备硬连线签名块和签名寄存器的内容之间进行硬件逻辑比较。 设备硬连线签名块是硬件实现的常数，不可用于加载IC的寄存器。 当硬件逻辑比较结果指示设备硬连线签名块等于签名寄存器的内容时​​，存储器块被验证为保持固定值。

    DATA ENCODING SCHEME TO REDUCE SENSE CURRENT
    5.
    发明申请
    DATA ENCODING SCHEME TO REDUCE SENSE CURRENT 有权
    数据编码方案降低感应电流

    公开(公告)号：US20110292711A1

    公开(公告)日：2011-12-01

    申请号：US13151230

    申请日：2011-06-01

    申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G11C17/16

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

    摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

    Data encoding scheme to reduce sense current
    6.
    发明授权
    Data encoding scheme to reduce sense current 有权
    减少感应电流的数据编码方案

    公开(公告)号：US07978493B1

    公开(公告)日：2011-07-12

    申请号：US12212801

    申请日：2008-09-18

    申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

    摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

    Data encoding scheme to reduce sense current
    7.
    发明授权
    Data encoding scheme to reduce sense current 有权
    减少感应电流的数据编码方案

    公开(公告)号：US08189362B2

    公开(公告)日：2012-05-29

    申请号：US13151230

    申请日：2011-06-01

    申请人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    发明人： Jun Pin Tan ,  Tze Swan Tan ,  Chuan Khye Chai ,  Boon Jin Ang ,  Kar Keng Chua

    IPC分类号： G11C17/00

    CPC分类号： G11C17/18 ,  G11C17/16

    摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

    摘要翻译： 公开了用于编码和解码熔丝数据以减少感测电流的技术。 编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。 各个保险丝的状态可以表示不同的逻辑状态。 熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。 熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。 与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。 解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。 熔丝数据的编码和解码可以减少熔丝感应电流。

    Dynamic real-time delay characterization and configuration
    8.
    发明授权
    Dynamic real-time delay characterization and configuration 有权
    动态实时延迟表征和配置

    公开(公告)号：US07787314B2

    公开(公告)日：2010-08-31

    申请号：US12208967

    申请日：2008-09-11

    申请人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

    发明人： Jun Pin Tan ,  Wei Yee Koay ,  Boon Jin Ang ,  Choong Kit Wong ,  Guang Sheng Soh

    IPC分类号： G11C7/10

    CPC分类号： H03K19/1735 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133

    摘要： In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.

    摘要翻译： 在掩模可编程集成电路（例如结构化ASIC）中，延迟链提供由掩模可编程开关设置的延迟。 延迟链接收输入以允许使用JTAG控制器覆盖延迟掩码编程的延迟。 这允许测试不同的延迟。 输入也可以由熔丝块提供，使得熔丝块可以覆盖掩模可编程开关，从而允许在掩模编程之后改变延迟。

    Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices
    9.
    发明授权
    Circuitry for facilitating performance of multiply-accumulate operations in programmable logic devices 有权
    用于促进在可编程逻辑器件中进行乘法累加操作的电路的电路

    公开(公告)号：US07565390B1

    公开(公告)日：2009-07-21

    申请号：US11089684

    申请日：2005-03-23

    申请人： Tat Mun Lui ,  Bee Yee Ng ,  Jun Pin Tan ,  Boon Jin Ang

    发明人： Tat Mun Lui ,  Bee Yee Ng ,  Jun Pin Tan ,  Boon Jin Ang

    IPC分类号： G06F7/48

    CPC分类号： G06F7/5443 ,  G06F7/4991 ,  H03K19/17704 ,  H03K19/17732

    摘要： In circuitry such as a programmable logic device (“PLD”), each of several multiplier blocks includes partial products generation circuitry and partial products addition circuitry. Two such multiplier blocks can be used together to provide multiply-accumulate (“MAC”) capability. The partial products addition circuitry in one of the paired blocks is used to add each successive product produced by the other paired block to a previous accumulation of products in the first-mentioned paired block. Provisions are also made for accumulating any overflow from operation of the partial products addition circuitry in the first-mentioned paired block.

    摘要翻译： 在诸如可编程逻辑器件（“PLD”）的电路中，几个乘法器块中的每一个包括部分乘积生成电路和部分乘积加法电路。 两个这样的乘法器块可以一起使用以提供乘法累加（“MAC”）能力。 一个配对块中的部分乘积加法电路用于将由另一个配对块产生的每个连续乘积加到先前提到的配对块中先前积累的乘积。 还提供了在第一提到的配对块中累积部分产品添加电路的操作的任何溢出的规定。

    Integrated circuit with configurable test pins
    10.
    发明授权
    Integrated circuit with configurable test pins 有权
    具有可配置测试引脚的集成电路

    公开(公告)号：US08327199B1

    公开(公告)日：2012-12-04

    申请号：US12718914

    申请日：2010-03-05

    申请人： Jayabrata Ghosh Dastidar ,  Chiew Khiang Kuit ,  Siew Ling Yeoh ,  Jun Pin Tan ,  Kok Sun Chia ,  Yee Liang Tan ,  Kar Keng Chua

    发明人： Jayabrata Ghosh Dastidar ,  Chiew Khiang Kuit ,  Siew Ling Yeoh ,  Jun Pin Tan ,  Kok Sun Chia ,  Yee Liang Tan ,  Kar Keng Chua

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3172 ,  G01R31/318516

    摘要： Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.

    摘要翻译： 公开了具有可配置测试引脚的集成电路（IC）和测试IC的方法。 IC具有可配置为测试输入引脚，测试输出引脚或用户I / O引脚的输入/输出（I / O）引脚。 选择器电路用于选择性地将I / O引脚路由和耦合到IC上的各种逻辑块和测试电路。 选择器电路还用于选择性地将用户输出或测试输出耦合到IC上的不同I / O引脚。 开关用于配置选择器电路并在IC内部路由测试信号。 交换机的不同配置决定信号的路由。 来自I / O引脚的测试输入信号可以被路由到IC内的任何测试电路，并且来自测试电路的测试输出信号可以被路由到IC上的任何I / O引脚。