公开(公告)号：US07026242B2

公开(公告)日：2006-04-11

申请号：US10802411

申请日：2004-03-16

申请人： Hong-Seong Son ,  Sang-Rok Hah ,  Il-Goo Kim ,  Jun-Hwan Oh

发明人： Hong-Seong Son ,  Sang-Rok Hah ,  Il-Goo Kim ,  Jun-Hwan Oh

IPC分类号： H01L21/4763

CPC分类号： H01L21/2885 ,  H01L21/76877

摘要： In a method for filling a hole with a metal, an insulating layer, a first mask layer and a second mask layer are successively formed on a semiconductor substrate. The first and second mask layers are etched using a photoresist pattern to form first and second masks. The first mask layer pattern is selectively etched using an etchant, the first mask layer pattern having a higher etching selectivity than the second layer pattern with respect to the etchant, to form a third mask layer pattern having a broadened opening. The insulating layer is etched using the second mask to form a hole in the insulating layer. A metal layer is formed in the hole and the third opening. The metal layer is planarized to form a metal plug buried in the hole without recesses or voids.

摘要翻译： 在用金属填充孔的方法中，在半导体衬底上依次形成绝缘层，第一掩模层和第二掩模层。 使用光致抗蚀剂图案蚀刻第一和第二掩模层以形成第一和第二掩模。 使用蚀刻剂选择性地蚀刻第一掩模层图案，第一掩模层图案相对于蚀刻剂具有比第二层图案更高的蚀刻选择性，以形成具有加宽开口的第三掩模层图案。 使用第二掩模蚀刻绝缘层，以在绝缘层中形成孔。 在孔和第三开口中形成金属层。 金属层被平坦化以形成埋在孔中的金属塞，而没有凹陷或空隙。

公开(公告)号：US20050090094A1

公开(公告)日：2005-04-28

申请号：US10970297

申请日：2004-10-21

申请人： Jun-Hwan Oh ,  Hong-Seong Son

发明人： Jun-Hwan Oh ,  Hong-Seong Son

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32134

摘要： A method of forming a conductive pattern includes preparing a semiconductor substrate having a conductive pattern, forming an interlayer dielectric pattern having an opening exposing the conductive pattern on the semiconductor substrate, forming a metal layer on the interlayer dielectric pattern to fill the opening, wet etching the metal layer, and polishing the metal layer to form a metal pattern filling the opening. The wet etching is done such that a top surface of the interlayer dielectric pattern is not exposed.

摘要翻译： 形成导电图案的方法包括制备具有导电图案的半导体衬底，形成具有露出半导体衬底上的导电图案的开口的层间电介质图案，在层间电介质图案上形成金属层以填充开口，湿蚀刻 金属层，并且抛光金属层以形成填充开口的金属图案。 进行湿蚀刻，使得层间电介质图案的顶表面不被暴露。

公开(公告)号：US20070122969A1

公开(公告)日：2007-05-31

申请号：US11627139

申请日：2007-01-25

申请人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

发明人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

IPC分类号： H01L21/8242

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814

摘要： A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

摘要翻译： 接触结构包括设置在半导体衬底的预定区域上的下导电图案。 下导电层在其顶表面的预定区域具有凹区。 嵌入导电层填充凹区域。 嵌入导电层的顶表面至少与下导电图案的平坦顶表面的高度一样高。 模具层设置成覆盖半导体衬底，下导电图案和嵌入导电层。 上部导电图案以凹版图案布置。 凹版图案设置在模具层中以暴露嵌入导电层的预定区域。

公开(公告)号：US07180188B2

公开(公告)日：2007-02-20

申请号：US10833548

申请日：2004-04-28

申请人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

发明人： Jung-Hwan Oh ,  Byung-Lyul Park ,  Hong-Seong Son

IPC分类号： H01L23/48

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76807 ,  H01L21/76814

摘要： A contact structure includes a lower conductive pattern disposed on a predetermined region of a semiconductor substrate. The lower conductive layer has a concave region at a predetermined region of a top surface thereof. An embedding conductive layer fills the concave region. The top surface of the embedding conductive layer is placed at least as high as the height of the flat top surface of the lower conductive pattern. A mold layer is disposed to cover the semiconductor substrate, the lower conductive pattern and the embedding conductive layer. An upper conductive pattern is arranged in an intaglio pattern. The intaglio pattern is disposed in the mold layer to expose a predetermined region of the embedding conductive layer.

摘要翻译： 接触结构包括设置在半导体衬底的预定区域上的下导电图案。 下导电层在其顶表面的预定区域具有凹区。 嵌入导电层填充凹区域。 嵌入导电层的顶表面至少与下导电图案的平坦顶表面的高度一样高。 模具层设置成覆盖半导体衬底，下导电图案和嵌入导电层。 上部导电图案以凹版图案布置。 凹版图案设置在模具层中以暴露嵌入导电层的预定区域。

公开(公告)号：US20050048875A1

公开(公告)日：2005-03-03

申请号：US10850688

申请日：2004-05-21

申请人： Ja-Eung Koo ,  Jong-Won Lee ,  Sung-Bae Lee ,  Duk-Ho Hong ,  Sang-Rok Hah ,  Hong-Seong Son

发明人： Ja-Eung Koo ,  Jong-Won Lee ,  Sung-Bae Lee ,  Duk-Ho Hong ,  Sang-Rok Hah ,  Hong-Seong Son

IPC分类号： B24B37/02 ,  B24B37/04 ,  B24B49/10 ,  B24B49/14 ,  B24B49/00 ,  B24B1/00

CPC分类号： B24B37/013 ,  B24B49/10 ,  B24B49/14

摘要： There is provided a chemical mechanical polishing apparatus, which may include a polishing table rotated by a polishing table motor and having a pad thereon, a carrier head located above the polishing table to be rotatable by the driving of a carrier head motor and having a wafer located under the bottom thereof, a slurry supplier for supplying a slurry to the upper portion of the polishing table, a first polishing end point detector for detecting a polishing end point through the temperature change of the temperature sensor, at least one temperature sensor for detecting the temperature of a polishing region (the wafer, the pad, and the slurry), and a second polishing end point detector for detecting a polishing end point from the changes of load current, voltage, and resistance of the carrier head motor. Further, instead of the second polishing end point detector, an optical signal polishing end point detector may be employed, for detecting the polishing end point by the light illuminated on the wafer and reflected from the wafer.

公开(公告)号：US07488235B2

公开(公告)日：2009-02-10

申请号：US11381415

申请日：2006-05-03

申请人： Moo-Yong Park ,  Sang-Rok Hah ,  Jong-Gyoon Kim ,  Hong-Seong Son ,  Ja-Hyung Han

发明人： Moo-Yong Park ,  Sang-Rok Hah ,  Jong-Gyoon Kim ,  Hong-Seong Son ,  Ja-Hyung Han

IPC分类号： B24B49/00

CPC分类号： B24B37/30 ,  B24B1/005 ,  B24B49/16

摘要： Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.

摘要翻译： 抛光装置和相关方法使用对准的第一和第二磁场源来通过选择性地和可控地产生驱避剂或两者之间的吸引力来调节由载体头部抵靠目标工件（例如晶片）施加的压缩力和/或压力 磁场源

公开(公告)号：US20070117378A1

公开(公告)日：2007-05-24

申请号：US11655159

申请日：2007-01-19

申请人： Sung-Bae Lee ,  Sang-Rok Hah ,  Hong-Seong Son

发明人： Sung-Bae Lee ,  Sang-Rok Hah ,  Hong-Seong Son

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/302

CPC分类号： H01L27/10885 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/66181

摘要： A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

摘要翻译： 一种用于制造半导体器件的方法包括在衬底上形成光致抗蚀剂图案，执行第一蚀刻工艺，其中使用光致抗蚀剂图案作为掩模形成初始沟槽，并且执行第二不同的蚀刻工艺以扩大初始沟槽。 因此，可以使用具有稳定结构的光致抗蚀剂图案来形成初始沟槽。 此后，使用具有基于其中形成初始沟槽的材料的组成的蚀刻溶液（例如硅衬底或绝缘膜）来扩大沟槽。 因此，可以在扩大的沟槽中形成金属布线，隔离膜或接触件到期望的尺寸。

公开(公告)号：US20060076034A1

公开(公告)日：2006-04-13

申请号：US11225504

申请日：2005-09-13

申请人： Chang-Hyeon Nam ,  Hong-Seong Son ,  Kyung-Hyun Kim

发明人： Chang-Hyeon Nam ,  Hong-Seong Son ,  Kyung-Hyun Kim

IPC分类号： B08B3/12 ,  C03C23/00 ,  B08B3/00

CPC分类号： H01L21/67051 ,  B08B3/12 ,  H01L21/02052 ,  Y10S134/902

摘要： A cleaning apparatus includes upper and lower nozzle assemblies supplying a cleaning liquid to edge and bottom sections of a semiconductor substrate. The upper nozzle assembly has a first nozzle supplying the cleaning liquid onto the edge section, and second and third nozzles supplying a nitrogen gas for preventing the cleaning liquid from moving into a center portion of the semiconductor substrate. The cleaning liquid supplied to the edge section flows from the edge section towards a side section of the semiconductor substrate due to the rotation of the semiconductor substrate. An ultrasonic wave generator is provided above the edge section for generating ultrasonic waves. The ultrasonic waves are applied to the cleaning liquid supplied onto the edge and bottom sections, thereby improving the cleaning efficiency. The cleaning apparatus has a guide to guide the cleaning liquid supplied to the edge section toward the side section. The cleaning apparatus may effectively remove impurities from the edge, side and bottom sections of the semiconductor substrate.

公开(公告)号：US20080166851A1

公开(公告)日：2008-07-10

申请号：US12030476

申请日：2008-02-13

申请人： Uk-Sun HONG ,  Sang-Rok Hah ,  Hong-Seong Son

发明人： Uk-Sun HONG ,  Sang-Rok Hah ,  Hong-Seong Son

IPC分类号： H01L21/02

CPC分类号： H01G4/33 ,  H01L21/31144 ,  H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention discloses a metal-insulator-metal (MIM) capacitor and a method for fabricating the MIM capacitor, comprising forming a bottom insulation layer, a capacitor electrode material layer, and a hard mask material layer on a semiconductor substrate having a metal wire thereon; forming a hard mask by etching the hard mask material layer using a photosensitive mask; forming a capacitor electrode by etching the capacitor electrode material layer using the hard mask as an etching mask; and forming a top insulation layer on an entire surface of the semiconductor.

摘要翻译： 本发明公开了一种金属绝缘体金属（MIM）电容器及其制造方法，包括在具有金属线的半导体基板上形成底部绝缘层，电容器电极材料层和硬掩模材料层 上; 通过使用感光掩模蚀刻硬掩模材料层来形成硬掩模; 通过使用硬掩模作为蚀刻掩模来蚀刻电容器电极材料层来形成电容器电极; 以及在半导体的整个表面上形成顶部绝缘层。

公开(公告)号：US07183226B2

公开(公告)日：2007-02-27

申请号：US10673873

申请日：2003-09-30

申请人： Sung-Bae Lee ,  Sang-Rok Hah ,  Hong-Seong Son

发明人： Sung-Bae Lee ,  Sang-Rok Hah ,  Hong-Seong Son

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L27/10885 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/66181

摘要： A method for use in manufacturing a semiconductor device includes forming a photoresist pattern on a substrate, performing first etching process in which an initial trench is formed using the photoresist pattern as a mask, and performing second distinct etching process to enlarge the initial trench. Thus, the initial trench can be formed using the photoresist pattern having a stable structure. Thereafter, the trench is enlarged using an etching solution having a composition based on the material in which the initial trench is formed, e.g., a silicon substrate or an insulation film. Therefore, a metal wiring, an isolation film or a contact can be formed in the enlarged trench to desired dimensions.

摘要翻译： 一种用于制造半导体器件的方法包括在衬底上形成光致抗蚀剂图案，执行第一蚀刻工艺，其中使用光致抗蚀剂图案作为掩模形成初始沟槽，并且执行第二不同的蚀刻工艺以扩大初始沟槽。 因此，可以使用具有稳定结构的光致抗蚀剂图案来形成初始沟槽。 此后，使用具有基于其中形成初始沟槽的材料的组成的蚀刻溶液（例如硅衬底或绝缘膜）来扩大沟槽。 因此，可以在扩大的沟槽中形成金属布线，隔离膜或接触件到期望的尺寸。