公开(公告)号：US20090098701A1

公开(公告)日：2009-04-16

申请号：US11974570

申请日：2007-10-15

申请人： Jurgen Faul ,  Martin Popp ,  Andrew Graham ,  Dongping Wu ,  Victor Verdugo

发明人： Jurgen Faul ,  Martin Popp ,  Andrew Graham ,  Dongping Wu ,  Victor Verdugo

IPC分类号： H01L21/336

CPC分类号： H01L21/26506 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/66621

摘要： The present invention provides a method of manufacturing an integrated circuit comprising the steps of: providing a semiconductor substrate, etching at least one trench into a surface of said semiconductor substrate, performing an ion implantation step, wherein a direction of said ion implantation step is parallel to a vertical centre line of said trench, and performing a single oxidation step to form a first oxide layer with a first layer thickness covering a bottom of said at least one trench and a second oxide layer with a second layer thickness covering the sidewalls of said at least one trench, wherein said first layer thickness differs from said second layer thickness.

摘要翻译： 本发明提供一种制造集成电路的方法，包括以下步骤：提供半导体衬底，将至少一个沟槽蚀刻到所述半导体衬底的表面中，执行离子注入步骤，其中所述离子注入步骤的方向是平行的 到所述沟槽的垂直中心线，并且执行单个氧化步骤以形成覆盖所述至少一个沟槽的底部的第一层厚度的第一氧化物层和覆盖所述至少一个沟槽的侧壁的第二层厚度的第二氧化物层 至少一个沟槽，其中所述第一层厚度与所述第二层厚度不同。

公开(公告)号：US20110222817A1

公开(公告)日：2011-09-15

申请号：US13123317

申请日：2009-10-06

申请人： Ingo Smaglinski ,  Thomas Petigk ,  Martin Popp ,  Samuel Brantzen ,  Thomas Paatzsch

发明人： Ingo Smaglinski ,  Thomas Petigk ,  Martin Popp ,  Samuel Brantzen ,  Thomas Paatzsch

IPC分类号： G02B6/35

CPC分类号： G02B6/4215 ,  G02B6/29365 ,  G02B6/4214

摘要： The present invention relates to a multiplexer/demultiplexer with a connection for inputting and/or outputting an optical signal which has signal components of different wavelengths, a carrier plate (8) with at least one wavelength-sensitive element (11), a focussing member (13) with at least two focussing elements (14, 14′) as well as a detector or signal-generator plate (1), on which at least two detectors (4) or signal generators are arranged. To achieve this, it is proposed according to the invention that the focussing member (13) has at least one fibre stop, preferably formed integrally with the focussing member for adjusting a waveguide, and is connected to the detector or signal-generator plate (1) or to the carrier plate (8) via an elastic connecting element (23).

摘要翻译： 本发明涉及具有用于输入和/或输出具有不同波长的信号分量的光信号的连接的多路复用器/解复用器，具有至少一个波长敏感元件（11）的载板（8），聚焦部件 （13）具有至少两个聚焦元件（14,14'）以及检测器或信号发生器板（1），其上布置有至少两个检测器（4）或信号发生器。 为了实现这一点，根据本发明提出，聚焦构件（13）具有至少一个光纤停止件，优选地与用于调节波导的聚焦构件整体形成，并且连接到检测器或信号发生器板（1） ）或通过弹性连接元件（23）连接到承载板（8）。

公开(公告)号：US20090302380A1

公开(公告)日：2009-12-10

申请号：US12134740

申请日：2008-06-06

申请人： Werner Graf ,  Lars Heineck ,  Martin Popp

发明人： Werner Graf ,  Lars Heineck ,  Martin Popp

IPC分类号： H01L27/105 ,  H01L21/762

CPC分类号： H01L21/76232 ,  H01L21/743 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891

摘要： In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

摘要翻译： 在一个实施例中，存储单元包括布置在半导体衬底中的位线和布置在位线附近的位线接触区域。 在形成在半导体衬底中的沟槽中的位线接触区域上方布置字线。 大致U形绝缘层布置在沟槽的底部区域中，并将位线和位线接触区域与字线分离。

公开(公告)号：US20080061340A1

公开(公告)日：2008-03-13

申请号：US11470792

申请日：2006-09-07

申请人： Lars Heineck ,  Martin Popp

发明人： Lars Heineck ,  Martin Popp

IPC分类号： H01L29/94

CPC分类号： H01L29/945 ,  H01L27/0207 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10891

摘要： A memory cell array having a plurality of memory cells is disclosed. In one embodiment, each memory cell includes a storage capacitor and an access transistor, a plurality of bit lines orientated in a first direction, a plurality of word lines orientated in a second direction, the second direction being perpendicular to the first direction, a semiconductor substrate with a surface, a plurality of active areas being formed in the semiconductor substrate, each active area extending in the second direction, the access transistors being partially formed in the active areas and electrically coupling corresponding ones of the storage capacitors to corresponding bit lines, wherein a gate electrode of each of the access transistors is connected with a corresponding word line, a capacitor dielectric of the storage capacitor has a relative dielectric constant of more than 8, and the word lines are disposed above the bit lines.

摘要翻译： 公开了一种具有多个存储单元的存储单元阵列。 在一个实施例中，每个存储单元包括存储电容器和存取晶体管，沿第一方向定向的多个位线，沿第二方向定向的多个字线，第二方向垂直于第一方向，半导体 具有表面的衬底，在半导体衬底中形成多个有源区域，每个有源区域在第二方向上延伸，存取晶体管部分地形成在有源区域中，并将对应的存储电容器电耦合到对应的位线， 其中每个存取晶体管的栅电极与对应的字线连接，所述存储电容器的电容电介质具有大于8的相对介电常数，并且所述字线位于所述位线之上。

公开(公告)号：US20070134871A1

公开(公告)日：2007-06-14

申请号：US11702162

申请日：2007-02-05

申请人： Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

发明人： Dietmar Temmler ,  Martin Gutsche ,  Martin Popp ,  Harald Seidl

IPC分类号： H01L21/8242

CPC分类号： H01L27/10867 ,  H01L27/10832 ,  H01L27/10864

摘要： Memory cells having trench capacitors, the trench capacitor being at least partially filled with a material which could not withstand high-temperature processes used during the fabrication of a memory chip without impairment of its electrical parameters. What is essential to the invention is that the material of the trench capacitor is introduced into the trench after the high-temperature processes. The method according to the invention makes it possible to use dielectric layers having large dielectric constants and electrode layers made of metallic material. The electrical properties of the trench capacitor are thus improved in comparison with known trench capacitors.

摘要翻译： 具有沟槽电容器的存储单元，沟槽电容器至少部分地填充有不能承受在制造存储器芯片期间使用的高温处理而不损害其电参数的材料。 本发明的重要内容是在高温处理之后将沟槽电容器的材料引入沟槽。 根据本发明的方法使得可以使用具有大介电常数的电介质层和由金属材料制成的电极层。 与已知的沟槽电容器相比，沟槽电容器的电性能得到改善。

公开(公告)号：US20060060734A1

公开(公告)日：2006-03-23

申请号：US10534341

申请日：2002-11-11

申请人： Martin Popp ,  Ingo Smaglinski ,  Jens Haase ,  Gerhard Himmelsbach

发明人： Martin Popp ,  Ingo Smaglinski ,  Jens Haase ,  Gerhard Himmelsbach

IPC分类号： E04G3/00

CPC分类号： G02B7/006 ,  G02B6/29367 ,  G02B6/32 ,  G02B6/3636 ,  G02B6/3652 ,  G02B6/3696 ,  G02B6/4214

摘要： The invention relates to a support element (1), for mounting at least two wave-modifying elements, with support of services, arranged parallel to each other. According to the invention, support element for mounting at least two wave-modifying elements and corresponding production method maybe achieved, whereby the support surfaces each have at least one opening and the openings are connected to each other by means of at least one through drilling.

摘要翻译： 本发明涉及一种支撑元件（1），用于安装至少两个波形修改元件，其具有彼此平行布置的服务支撑。 根据本发明，可以实现用于安装至少两个波浪修改元件的支撑元件和相应的制造方法，由此支撑表面各自具有至少一个开口，并且开口通过至少一个穿孔相互连接。

公开(公告)号：US07012289B2

公开(公告)日：2006-03-14

申请号：US10348148

申请日：2003-01-21

申请人： Martin Popp ,  Dietmar Temmler

发明人： Martin Popp ,  Dietmar Temmler

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10867 ,  H01L27/10832

摘要： A memory cell has a trench capacitor, in which the area required over a terminal area of the trench capacitor is advantageously reduced by the formation of a particularly thin insulation collar. The insulation collar is reduced to such an extent that although a lateral current is prevented, the formation of a parasitic field-effect transistor is permitted. In order that, however, overall no current flows via the parasitic field-effect transistor, a second parasitic field-effect transistor is disposed in a manner connected in series, but is not turned on. This is achieved by the formation of a thicker second insulation collar that isolates the filling of the trench capacitor from the surrounding substrate.

摘要翻译： 存储单元具有沟槽电容器，其中通过形成特别薄的绝缘套圈有利地减小了沟槽电容器的端子区域所需的面积。 绝缘套环被减小至尽可能防止横向电流的程度，允许形成寄生场效应晶体管。 然而，为了使整个无电流通过寄生场效应晶体管流过，第二寄生场效应晶体管以串联连接的方式设置，但不导通。 这是通过形成较厚的第二绝缘套圈来实现的，其将沟槽电容器的填充与周围衬底隔离。

公开(公告)号：US06956260B2

公开(公告)日：2005-10-18

申请号：US10463019

申请日：2003-06-17

申请人： Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

发明人： Dirk Manger ,  Till Schlösser ,  Martin Popp ,  Michael Sesterhenn

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10891

摘要： In semiconductor memories, in particular DRAMs, the memory cells of which have vertical transistors at vertical lands formed from substrate material, gate electrodes are formed as spacers which run around the land. The gate electrodes of adjacent memory cells conventionally have to be retroactively connected to form word lines. It is known to fill spaces between adjacent lands with an oxide, with the result that the spacers are formed directly as word lines but only cover two side walls of a land. Two transistors which are connected in parallel are formed at these side walls instead of a single transistor, since the gate electrode does not run around the land. The invention proposes a method for fabricating a semiconductor memory in which all four side walls of a land are covered by the word lines and at the same time lands of adjacent memory cells are connected to one another by the word lines.

摘要翻译： 在半导体存储器中，特别是DRAM，其存储单元在由衬底材料形成的垂直焊盘处具有垂直晶体管，栅电极形成为围绕焊盘运行的间隔件。 相邻存储单元的栅电极通常必须追溯地连接以形成字线。 已知用相邻的焊盘之间的空间填充氧化物，结果是间隔件直接形成为字线，而仅覆盖焊盘的两个侧壁。 并联连接的两个晶体管形成在这些侧壁而不是单个晶体管，因为栅电极不会绕着焊盘运行。 本发明提出一种半导体存储器的制造方法，其中，由字线覆盖焊盘的四个侧壁，同时通过字线将相邻存储单元的焊盘相互连接。

公开(公告)号：US06924225B2

公开(公告)日：2005-08-02

申请号：US10893561

申请日：2004-07-16

申请人： Martin Popp ,  Dietmar Temmler

发明人： Martin Popp ,  Dietmar Temmler

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/76807 ,  H01L21/76838 ,  H01L21/823425 ,  H01L21/823475 ,  H01L2221/1026

摘要： An electrically conductive contact can be used to connect an integrated component to an interconnect. A sacrificial layer is deposited on a liner and planarized until a surface of the integrated component is uncovered. The sacrificial layer is patterned to define the later contacts. The layer is covered in a partial region above contact connection regions. An interlevel insulator is deposited and patterned, so that the sacrificial layer can then be stripped out from the partial region. After the removal of the liner, a conductive layer is deposited into the cavity formed as a result of the stripping-out process on the uncovered contact connection regions and optionally into trenches formed at the outset within the interlevel insulator.

公开(公告)号：US06835666B2

公开(公告)日：2004-12-28

申请号：US10291070

申请日：2002-11-08

申请人： Martin Popp

发明人： Martin Popp

IPC分类号： H01L21302

CPC分类号： H01L21/3086

摘要： A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second lithographic process sequence in order to pattern the sacrificial layer in a first and a second direction. A hard mask layer is subsequently applied in order to completely enclose the patterned sacrificial layer. Finally, the sacrificial layer is then removed from the hard mask layer.

摘要翻译： 通过在半导体晶片上施加牺牲层来制造掩模。 然后借助于第一和第二光刻工艺顺序处理牺牲层，以便沿第一和第二方向图案化牺牲层。 随后施加硬掩模层以完全包围图案化的牺牲层。 最后，从硬掩模层去除牺牲层。