公开(公告)号：US20150179540A1

公开(公告)日：2015-06-25

申请号：US14326925

申请日：2014-07-09

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Katsuhiro YASUI

IPC分类号： H01L23/36 ,  H01L23/498

CPC分类号： H01L23/495 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/4334 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having a first surface and a second surface. A semiconductor chip is disposed on the first surface of the substrate. A first metal pattern is disposed on a central portion of the second surface. A second metal pattern is disposed on the second surface and spaced from the first metal pattern. A thermal conducting material is affixed to the first and second metal patterns. The first metal pattern has no two outer edges that meet to form an angle that is 90° or less, and the second metal pattern is between the first metal pattern and an outer edge of the substrate.

摘要翻译： 半导体器件包括具有第一表面和第二表面的衬底。 半导体芯片设置在基板的第一表面上。 第一金属图案设置在第二表面的中心部分上。 第二金属图案设置在第二表面上并与第一金属图案间隔开。 导热材料固定在第一和第二金属图案上。 第一金属图案没有两个外边缘相遇以形成90°或更小的角度，并且第二金属图案位于第一金属图案和基板的外边缘之间。

公开(公告)号：US20170194296A1

公开(公告)日：2017-07-06

申请号：US15231444

申请日：2016-08-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Katsuhiro YASUI

IPC分类号： H01L25/07 ,  H01L23/04 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00

CPC分类号： H01L25/072 ,  H01L23/041 ,  H01L23/053 ,  H01L23/24 ,  H01L23/28 ,  H01L23/29 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85399

摘要： A semiconductor module includes an insulating substrate. A first and a second metal member are joined respectively to a side surface of the substrate. Each metal member has an opening formed therein. A first and a second conductive layer are on the upper surface of the substrate and spaced apart from each other. A first semiconductor chip is mounted on the first conductive layer. A first electrode of the first semiconductor chip is electrically connected to the first conductive layer, and a second electrode is electrically connected to the second conductive layer. A first terminal is electrically connected to the first conductive layer, and a second terminal is electrically connected to the second conductive layer. A sealing resin is disposed on the upper surface of the substrate to cover the first conductive layer, the second conductive layer, the first semiconductor chip, and portions of the first and second terminals.