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公开(公告)号：US09684602B2
公开(公告)日：2017-06-20
申请号：US14931724
申请日：2015-11-03
发明人： Seiji Maeda
IPC分类号： G06F12/08 , G06F12/0875
CPC分类号： G06F12/0875 , G06F12/0868 , G06F12/0888 , G06F12/122 , G06F12/123 , G06F2212/1016 , G06F2212/1021 , G06F2212/1028 , G06F2212/312 , G06F2212/45 , Y02D10/13
摘要： A memory access control device of an embodiment includes a data memory configured to record information of an access request relating to reading and writing of data to a main memory, and a controller configured to receive notification of the access request and select an access destination with reference to recording content of the data memory. When history of a request for write access and history of a request for read access to an address designated by the access request are recorded in the data memory, the controller selects a cache memory as the access destination, and otherwise, selects the main memory as the access destination.
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公开(公告)号：US09600234B2
公开(公告)日：2017-03-21
申请号：US14643279
申请日：2015-03-10
发明人： Seiji Maeda
CPC分类号： G06F7/483 , G06F7/49947
摘要： A floating-point arithmetic device of an embodiment includes: a first functional unit configured to receive first input data to execute first arithmetic operation in a first rounding mode; a second functional unit configured to receive second input data to execute second arithmetic operation in a second rounding mode; a first output circuit capable of selectively outputting a first output or a first arithmetic operation result of the first arithmetic operation, the first output obtained by halving a first value obtained by adding a second arithmetic operation result of the second arithmetic operation to the first arithmetic operation result; and a second output circuit capable of selectively outputting a second output or the second arithmetic operation result, the second output obtained by halving a second value obtained by subtracting the second arithmetic operation result from the first arithmetic operation result.
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公开(公告)号：US09990288B2
公开(公告)日：2018-06-05
申请号：US14484093
申请日：2014-09-11
发明人： Hiroyuki Usui , Seiji Maeda
IPC分类号： G06F12/08 , G06F12/0813
CPC分类号： G06F12/0813 , G06F2212/154 , G06F2212/305
摘要： An information processing device of an embodiment has an input unit, a storage unit, a read control unit, and a write control unit. A read request and a write request are input to the input unit. The storage unit stores management information. When the read request is input, the read control unit reads read data including the management information from the storage unit, references the management information, and outputs only non-zero data included in a predetermined range of a block row. The write control unit writes only non-zero data to the storage unit and updates the management information immediately before a start position of the continuous non-zero data started from a largest position in the continuous non-zero data started from a position smaller than the predetermined range, a last management information stored in the predetermined range, and the last management information in the predetermined range.
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公开(公告)号：US09619386B2
公开(公告)日：2017-04-11
申请号：US14727229
申请日：2015-06-01
发明人： Seiji Maeda
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0815 , G06F13/16 , G06F9/30 , G06F12/084
CPC分类号： G06F12/0831 , G06F9/30087 , G06F12/0815 , G06F12/084 , G06F13/1657 , G06F13/1689 , G06F2212/621
摘要： According to an embodiment, a synchronization variable monitoring device includes: an address comparator configured to compare a received address included in an Invalidate Request, and an address that is set as an address of synchronization variable data upon receiving the Invalidate Request; a readout circuit configured to read out data of the address of the synchronization variable data when the received address and the address of the synchronization variable data coincide with each other; a conditional variable comparator configured to determine whether or not a predetermined condition is satisfied based on the data read out by the readout circuit; and a synchronization completion flag register configured to output a synchronization signal indicating that a synchronization condition is satisfied when the conditional variable comparator determines that the predetermined condition is satisfied.
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公开(公告)号：US20170017573A1
公开(公告)日：2017-01-19
申请号：US14942535
申请日：2015-11-16
发明人： Seiji Maeda
CPC分类号： G06F12/0804 , G06F12/0871 , G06F12/0888 , G06F12/126 , G06F2212/1016
摘要： A data access control apparatus of an embodiment includes an update region management apparatus including an update region management unit configured to record, in response to a writing request for data from an input apparatus, management information of a first address region in which the data is stored, a reading request management unit configured to record a second address specified in a reading request from a storage apparatus and a control unit configured to receive the writing request and the reading request, and control processing of the reading request and updating of the update region management unit and the reading request management unit.
摘要翻译： 实施例的数据访问控制装置包括更新区域管理装置，其包括更新区域管理单元，其被配置为响应于来自输入装置的数据的写入请求而记录数据存储在其中的第一地址区域的管理信息 ，读取请求管理单元，被配置为从存储装置记录在读取请求中指定的第二地址，以及控制单元，被配置为接收所述写入请求和所述读取请求，以及所述读取请求的控制处理和所述更新区域管理 单元和阅读请求管理单元。
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公开(公告)号：US09483442B2
公开(公告)日：2016-11-01
申请号：US14194471
申请日：2014-02-28
发明人： Seiji Maeda , Hiroyuki Usui
CPC分类号： G06F17/16
摘要： According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.
摘要翻译： 根据实施例，执行矩阵运算的矩阵运算装置包括多个节点，所述节点包括：被配置为对作为列数据执行第一输入的第一操作的乘法器和作为矩阵运算的行数据的第二输入 以及矩阵运算的运算结果的输出要素分量; 以及累加器，被配置为执行所述乘法器的运算结果的累加。
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公开(公告)号：US20150081752A1
公开(公告)日：2015-03-19
申请号：US14194471
申请日：2014-02-28
发明人： Seiji Maeda , Hiroyuki Usui
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.
摘要翻译： 根据实施例，执行矩阵运算的矩阵运算装置包括多个节点，所述节点包括：被配置为对作为列数据执行第一输入的第一操作的乘法器和作为矩阵运算的行数据的第二输入 以及矩阵运算的运算结果的输出要素分量; 以及累加器，被配置为执行所述乘法器的运算结果的累加。
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公开(公告)号：US09081711B2
公开(公告)日：2015-07-14
申请号：US14090428
申请日：2013-11-26
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。
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公开(公告)号：US20140164702A1
公开(公告)日：2014-06-12
申请号：US14090428
申请日：2013-11-26
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
摘要翻译： 实施例提供了一种虚拟地址高速缓存存储器，包括：TLB虚拟页面存储器，被配置为当对TLB的重写发生时，重写入口数据; 数据存储器，被配置为使用虚拟页标签或页偏移来保存高速缓存数据作为高速缓存索引; 高速缓存状态存储器，被配置为与高速缓存索引相关联地保存存储在数据存储器中的高速缓存数据的高速缓存状态; 第一物理地址存储器，被配置为当对所述TLB的重写发生时，重写所保持的物理地址; 以及第二物理地址存储器，被配置为当在发生对TLB的重写之后将高速缓存数据写入数据存储器时，重写保持的物理地址。
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公开(公告)号：US20170255577A1
公开(公告)日：2017-09-07
申请号：US15271689
申请日：2016-09-21
发明人： Seiji Maeda , Hiroyuki Usui
IPC分类号： G06F13/28 , G06F12/0811 , G06F12/1081 , G06F12/1018
CPC分类号： G06F13/28 , G06F12/0811 , G06F12/1018 , G06F12/1081 , G06F2212/283
摘要： A data transfer apparatus according to an embodiment includes: a first main memory configured to store first data to be used by a first processor; a first hash table in which a hash value and address information of the first data stored in the first main memory are registered; and a data transfer unit configured to transfer data having a hash value not registered in the first hash table from among second data stored in a second main memory from the second main memory to the first main memory.
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