公开(公告)号：US20170271348A1

公开(公告)日：2017-09-21

申请号：US15267776

申请日：2016-09-16

Applicant: Kabushiki Kaisha Toshiba

Inventor： Fumitaka ARAI ,  Tatsuya KATO ,  Satoshi NAGASHIMA ,  Katsuyuki SEKINE ,  Yuta WATANABE ,  Keisuke KIKUTANI ,  Atsushi MURAKOSHI

IPC: H01L27/115 ,  H01L21/28 ,  H01L21/768 ,  H01L23/535 ,  H01L29/788 ,  H01L21/3105

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/31051 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/535 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L29/7883 ,  H01L29/7889

Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.

公开(公告)号：US20160268275A1

公开(公告)日：2016-09-15

申请号：US14837306

申请日：2015-08-27

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yuta WATANABE ,  Takeshi ISHIZAKI ,  Kana HIRAYAMA ,  Kenji AOYAMA

IPC: H01L27/115

CPC classification number: H01L27/11521 ,  H01L29/40114

Abstract: A non-volatile memory device includes a first semiconductor body extending in a first direction, an electrode extending in a second direction intersecting the first direction, a charge storage layer provided between the first semiconductor body and the electrode, and a first insulating layer provided between the electrode and the charge storage layer. The electrode includes a first layer, a second layer and a third layer. The first layer is provided on the first insulating layer and includes tungsten. The second layer is provided on the first layer and includes tungsten nitride. The third layer is provided on the second layer and includes tungsten.

Abstract translation: 非易失性存储器件包括沿第一方向延伸的第一半导体本体，沿与第一方向相交的第二方向延伸的电极，设置在第一半导体本体和电极之间的电荷存储层，以及设置在第一绝缘层之间的第一绝缘层 电极和电荷存储层。 电极包括第一层，第二层和第三层。 第一层设置在第一绝缘层上并包括钨。 第二层设置在第一层上并且包括氮化钨。 第三层设置在第二层上并且包括钨。

公开(公告)号：US20170263615A1

公开(公告)日：2017-09-14

申请号：US15449481

申请日：2017-03-03

Applicant: Kabushiki Kaisha Toshiba

Inventor： Kohei SAKAIKE ,  Toshiyuki IWAMOTO ,  Tatsuya KATO ,  Keisuke KlKUTANI ,  Fumitaka ARAI ,  Satoshi NAGASHIMA ,  Koichi SAKATA ,  Yuta WATANABE

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.

公开(公告)号：US20170263613A1

公开(公告)日：2017-09-14

申请号：US15254014

申请日：2016-09-01

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Atsushi MURAKOSHI ,  Yasuhito YOSHIMIZU ,  Tomofumi INOUE ,  Tatsuya KATO ,  Yuta WATANABE ,  Fumitaka ARAI

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/1157 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/7926

Abstract: According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.

公开(公告)号：US20150262832A1

公开(公告)日：2015-09-17

申请号：US14479590

申请日：2014-09-08

Applicant: Kabushiki Kaisha Toshiba

Inventor： Keisuke KIKUTANI ,  Yuta WATANABE ,  Kazunori NISHIKAWA

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/32139 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31122 ,  H01L27/11504 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes manufacturing a mask pattern and forming an interconnection using the mask pattern. The manufacturing the mask pattern includes forming a first pattern of a first material, depositing a second material over the first pattern, forming a first sidewall film on sidewalls of the first pattern by a first etchback, depositing a third material over the first sidewall film, forming a second sidewall film on sidewalls of the first sidewall film by a second etchback, adjusting the first pattern and second sidewall film so as to have the same height, and selectively removing the first sidewall film. The first pattern has a line width of a first width equal to the thicknesses of the first and second sidewall films. The mask pattern includes a line-and-space having a line width and a space equal to the first width, respectively.

Abstract translation: 根据实施例，半导体器件的制造方法包括制造掩模图案并使用掩模图案形成互连。 制造掩模图案包括形成第一材料的第一图案，在第一图案上沉积第二材料，通过第一回蚀在第一图案的侧壁上形成第一侧壁膜，在第一侧壁膜上沉积第三材料， 通过第二回蚀在第一侧壁膜的侧壁上形成第二侧壁膜，调节第一图案和第二侧壁膜以具有相同的高度，以及选择性地去除第一侧壁膜。 第一图案具有等于第一和第二侧壁膜的厚度的第一宽度的线宽。 掩模图案包括分别具有线宽和等于第一宽度的空间的线和空间。

公开(公告)号：US20170263637A1

公开(公告)日：2017-09-14

申请号：US15267722

申请日：2016-09-16

Applicant: Kabushiki Kaisha Toshiba

Inventor： Koichi SAKATA ,  Yuta WATANABE ,  Keisuke KlKUTANI ,  Satoshi NAGASHIMA ,  Fumitaka ARAI ,  Toshiyuki IWAMOTO

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/31111 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.

公开(公告)号：US20170012050A1

公开(公告)日：2017-01-12

申请号：US14840345

申请日：2015-08-31

Applicant: Kabushiki Kaisha Toshiba

Inventor： Tatsuya KATO ,  Fumitaka ARAI ,  Satoshi NAGASHIMA ,  Katsuyuki SEKINE ,  Yuta WATANABE ,  Keisuke KIKUTANI ,  Atsushi MURAKOSHI

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/2481 ,  H01L29/7889

Abstract: A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.

Abstract translation: 根据一个实施例的半导体存储器件包括沿着第一方向延伸并且沿着与第一方向交叉的第二方向排列的多个第一互连件，沿着第一方向排列成沿着第一方向排列的多个半导体柱 第一互连并沿与第一方向和第二方向交叉的第三方向延伸;第一电极，设置在所述半导体柱之一和所述第一互连中的一个之间，设置在所述第一电极和所述第一互连中的一个之间的第一绝缘膜， 第一绝缘构件，其设置在所述第一方向上的所述半导体柱之间并且在所述第三方向上延伸并且不通过所述第一绝缘膜与所述第一互连相对。