公开(公告)号：US20250104759A1

公开(公告)日：2025-03-27

申请号：US18819770

申请日：2024-08-29

Applicant: Kioxia Corporation

Inventor： Tsuneo Inaba ,  Takayuki Miyazaki ,  Shinji Miyano

IPC: G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099

Abstract: A memory device includes a transistor, a capacitor, a plate line, and a bit line. The transistor includes an oxide semiconductor and includes a first end, a second end, and a gate. The capacitor includes a third end and a fourth end. The fourth end is coupled to the second end. The plate line is coupled to the third end. The bit line is coupled to the first end. A second voltage lower than a first voltage is applied to the plate line during a first period over which the first voltage is applied to the gate. A fourth voltage higher than the second voltage is applied to the plate line during at least a part of a second period over which a third voltage lower than the first voltage is applied to the gate.

公开(公告)号：US12068031B2

公开(公告)日：2024-08-20

申请号：US17901239

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Jun Deguchi ,  Daisuke Miyashita ,  Atsushi Kawasumi ,  Hidehiro Shiga ,  Shinji Miyano ,  Shinichi Sasaki

IPC: G11C16/08 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

公开(公告)号：US11676677B2

公开(公告)日：2023-06-13

申请号：US17377247

申请日：2021-07-15

Applicant: KIOXIA CORPORATION

Inventor： Yoshihiro Ueda ,  Shinji Miyano

IPC: G11C19/08 ,  G11C11/16

CPC classification number: G11C19/0841 ,  G11C19/0833 ,  G11C11/161

Abstract: A magnetic storage device includes a magnetic body including first and second magnetic regions and a magnetic connection region that connects the first and second magnetic regions, and in which a plurality of magnetic domains each storing information by a magnetization direction thereof is formed, a read element that is electrically connected to the magnetic connection region and by which a magnetization direction of one of the magnetic domains is read, and a write element by which a magnetic domain having a magnetization direction is formed in the magnetic body according to information to be stored. The magnetic domains formed in each of the first and second magnetic regions are shifted in a predetermined direction in response to current that flows through the corresponding one of the first and second magnetic regions.

公开(公告)号：US11665882B2

公开(公告)日：2023-05-30

申请号：US17012676

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Masaharu Wada ,  Mutsumi Okajima ,  Tsuneo Inaba ,  Shinji Miyano

IPC: H01L27/10 ,  H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10808 ,  H01L27/1082 ,  H01L27/10832 ,  H01L27/10897 ,  G11C11/407

Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.