公开(公告)号：US11978501B2

公开(公告)日：2024-05-07

申请号：US17842516

申请日：2022-06-16

Applicant: Kioxia Corporation

Inventor： Akiyuki Murayama ,  Kikuko Sugimae ,  Katsuya Nishiyama ,  Yusuke Arayashiki ,  Motohiko Fujimatsu ,  Kyosuke Sano ,  Noboru Shibata

IPC: G11C11/00 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4099

CPC classification number: G11C11/4085 ,  G11C5/063 ,  G11C11/4074 ,  G11C11/4099

Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.

公开(公告)号：US11963353B2

公开(公告)日：2024-04-16

申请号：US17460944

申请日：2021-08-30

Applicant: Kioxia Corporation

Inventor： Yusuke Arayashiki

IPC: H10B43/27 ,  H01L21/28 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L29/40114 ,  H01L29/40117 ,  H10B41/10 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor storage device includes a third semiconductor layer and a fourth semiconductor layer. The third semiconductor layer has a first width; the third semiconductor layer and a first insulating layer are disposed apart with a first distance; the third semiconductor layer and a second insulating layer are disposed apart with a second distance; the fourth semiconductor layer has a second width; the fourth semiconductor layer and the first insulating layer are disposed apart with a third distance; and the fourth semiconductor layer and the second insulating layer are disposed apart with a fourth distance. A shorter one of the first distance and the second distance is shorter than a shorter one of the third distance and the fourth distance, and the first width is larger than the second width.

公开(公告)号：US11495292B2

公开(公告)日：2022-11-08

申请号：US17195994

申请日：2021-03-09

Applicant: Kioxia Corporation

Inventor： Kikuko Sugimae ,  Yusuke Arayashiki

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US11744164B2

公开(公告)日：2023-08-29

申请号：US14631242

申请日：2015-02-25

Applicant: Kioxia Corporation

Inventor： Tomohito Kawashima ,  Takahiro Nonaka ,  Yusuke Arayashiki ,  Takayuki Ishikawa

IPC: H01L45/00 ,  H01L27/24 ,  H10N70/00 ,  H10N70/20 ,  H10B63/00

CPC classification number: H10N70/826 ,  H10N70/011 ,  H10N70/24 ,  H10N70/245 ,  H10N70/841 ,  H10N70/8416 ,  H10N70/8833 ,  H10B63/84

Abstract: According to one embodiment, a resistive random access memory device includes a first electrode and a second electrode. The resistive random access memory device also includes a resistance change layer connected between the first electrode and the second electrode. The resistive random access memory device also includes a conductive layer connected in series to the resistance change layer between the first electrode and the second electrode. The resistive random access memory device in which the conductive layer includes a plurality of first material layers including a first material and a plurality of second material layers including a second material which is different from the first material.

公开(公告)号：US11972796B2

公开(公告)日：2024-04-30

申请号：US17960660

申请日：2022-10-05

Applicant: Kioxia Corporation

Inventor： Kikuko Sugimae ,  Yusuke Arayashiki

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  H10B63/84 ,  H10N70/063 ,  H10N70/245 ,  H10N70/8416 ,  H10N70/883 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/71 ,  H10N70/826 ,  H10N70/8833 ,  H10N70/8836

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US11706921B2

公开(公告)日：2023-07-18

申请号：US17190871

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Yosuke Murakami ,  Satoshi Nagashima ,  Nobuyuki Momo ,  Takayuki Ishikawa ,  Yusuke Arayashiki

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  G11C7/18 ,  H01L23/00 ,  H10B41/10 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C7/18 ,  H01L24/46 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.

公开(公告)号：US11417669B2

公开(公告)日：2022-08-16

申请号：US17010776

申请日：2020-09-02

Applicant: KIOXIA CORPORATION

Inventor： Yefei Han ,  Yusuke Arayashiki

IPC: H01L27/11 ,  H01L27/11521 ,  H01L23/00 ,  H01L27/11519

Abstract: A semiconductor memory device includes a semiconductor pillar including a semiconductor layer and extending along a first direction, a first wiring extending along a second direction crossing the first direction, a first electrode between the semiconductor pillar and the first wiring, a first insulating layer between the first electrode and the first wiring and adjacent to the first electrode, a second insulating layer between the first insulating layer and the first wiring and adjacent to the first insulating layer, the second insulating layer having a higher dielectric constant than the first insulating layer, and a third insulating layer between the second insulating layer and the first wiring. A shortest distance between the second insulating layer and the semiconductor layer in the second direction is greater than a shortest distance between the first electrode and the semiconductor layer in the second direction.