公开(公告)号：US06321360B1

公开(公告)日：2001-11-20

申请号：US09580180

申请日：2000-05-26

Applicant: Kan Takeuchi ,  Hiroyuki Tanikawa

Inventor： Kan Takeuchi ,  Hiroyuki Tanikawa

IPC: G11C2900

CPC classification number: G06F11/106

Abstract: A system with a ferroelectric memory has a low probability of soft error thereby decreasing the possibility of serious damage to the system that might result from soft errors. The ferroelectric memory is provided with an overwrite-inhibited memory block 122 for storing this OS (Operating System) and applications, and an overwrite-free memory block 123 which is a work area. The overwrite-inhibited memory block 122 includes a parity bit storage 125. A process for checking and correcting error performed about one a day. A command for starting the error checking and correcting procedures is triggered by a switch such as power source switch. When an error occurs in the ferroelectric memory 120, it is possible to recover the function of the system.

Abstract translation: 具有铁电存储器的系统具有低误差概率，从而降低了可能由软错误导致的系统严重损坏的可能性。 铁电存储器设置有用于存储该OS（操作系统）和应用的重写禁止存储器块122和作为工作区域的无覆盖存储器块123。 重写禁止存储器块122包括奇偶校验位存储器125.用于检查和校正每天约一个执行的错误的处理。 启动错误检查和纠正程序的命令由电源开关等开关触发。 当铁电存储器120发生错误时，可以恢复系统的功能。

公开(公告)号：US6131177A

公开(公告)日：2000-10-10

申请号：US932957

申请日：1997-09-18

Applicant: Kan Takeuchi ,  Hiroyuki Tanikawa

Inventor： Kan Takeuchi ,  Hiroyuki Tanikawa

IPC: G06F12/16 ,  G06F11/10 ,  G11C11/22 ,  G11C11/401 ,  G11C14/00 ,  G11C29/42 ,  G11C29/00

CPC classification number: G06F11/106

Abstract: A system with a ferroelectric memory has a low probability of soft error thereby decreasing the possibility of serious damage to the system that might result from soft errors. The ferroelectric memory is provided with an overwrite-inhibited memory block 122 for storing the OS (Operating System) and applications, and an overwrite-free memory block 123 which is a work area. The overwrite-inhibited memory block 122 includes a parity bit storage 125. A process for checking and correcting error performed about once a day. A command for starting the error checking and correcting procedures is triggered by a switch such as power source switch. When an error occurs in the ferroelectric memory 120, it is possible to recover the function of the system.

Abstract translation: 具有铁电存储器的系统具有低误差概率，从而降低了可能由软错误导致的系统严重损坏的可能性。 铁电存储器设置有用于存储OS（操作系统）和应用的重写禁止存储器块122以及作为工作区域的无覆盖存储器块123。 重写禁止存储器块122包括奇偶校验位存储器125.用于检查和校正每天大约执行一次的错误的处理。 启动错误检查和纠正程序的命令由电源开关等开关触发。 当铁电存储器120发生错误时，可以恢复系统的功能。

公开(公告)号：US20140151094A1

公开(公告)日：2014-06-05

申请号：US13824821

申请日：2012-05-25

Applicant: Kan Takeuchi ,  Etsuko Suzuki ,  Kunihiro Morinaga ,  Kazuo Arita

Inventor： Kan Takeuchi ,  Etsuko Suzuki ,  Kunihiro Morinaga ,  Kazuo Arita

IPC: H05K1/03 ,  C09D167/00 ,  H05K3/00 ,  C08G63/60

CPC classification number: H05K3/00 ,  C08G8/32 ,  C08G59/4223 ,  C08G63/133 ,  C08G63/605 ,  C08J5/24 ,  C09D161/14 ,  C09D167/00 ,  H01L23/29 ,  H01L2924/0002 ,  H05K1/0353 ,  Y10T428/2915 ,  Y10T428/31529 ,  Y10T442/2475 ,  C08L63/00 ,  H01L2924/00

Abstract: A low dielectric constant, a low dielectric loss tangent, and heat resistance are achieved. An active ester resin that has a resin structure produced by reacting a polyfunctional phenolic compound (a1) with a monofunctional aromatic carboxylic acid or its chloride (a2) and an aromatic dicarboxylic acid or its chloride (a3). The polyfunctional phenolic compound (a1) is represented by structural formula (1) below: (where Ar represents a benzene ring, a naphthalene ring, a benzene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, or a naphthalene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, X represents a methylene group, a divalent cyclic aliphatic hydrocarbon group, a phenylene dimethylene group, or a biphenylene-dimethylene group, and n represents the number of repeating units and the average thereof is in a range of 0.5 to 10).

Abstract translation: 实现了低介电常数，低介电损耗角正切和耐热性。 具有通过使多官能性酚化合物（a1）与单官能芳族羧酸或其氯化物（a2）和芳香族二羧酸或其氯化物（a3）反应而制造的树脂结构的活性酯树脂。 多官能酚类化合物（a1）由下述结构式（1）表示：（其中Ar表示苯环，萘环，被碳原子数1〜4的烷基核取代的苯环或萘环 被具有1至4个碳原子的烷基核取代，X表示亚甲基，二价环状脂族烃基，亚苯基二亚甲基或亚联苯基 - 二亚甲基，n表示重复单元的数量和平均 在0.5〜10的范围内。

公开(公告)号：US07977238B2

公开(公告)日：2011-07-12

申请号：US12764411

申请日：2010-04-21

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L21/4763

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 公开了一种用于制造具有多层埋置布线的半导体集成电路器件的制造技术，并且防止了在其底部连接到埋地布线的插头与嵌入布线之间的界面处的应力迁移引起的不连续性的发生，以及 埋地线。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US5955896A

公开(公告)日：1999-09-21

申请号：US606852

申请日：1996-02-26

Applicant: Masashi Horiguchi ,  Jun Etoh ,  Takeshi Sakata ,  Kan Takeuchi ,  Katsumi Matsuno ,  Masakazu Aoki

Inventor： Masashi Horiguchi ,  Jun Etoh ,  Takeshi Sakata ,  Kan Takeuchi ,  Katsumi Matsuno ,  Masakazu Aoki

IPC: H03K19/0175 ,  G11C11/407 ,  G11C11/408 ,  H03K5/24 ,  H03K5/20

CPC classification number: H03K5/2481

Abstract: In an input circuit for semiconductor devices, such as an address buffer, an arrangement is provided which obviates the timing margin from capture of an input signal to its latching and outputting, thereby increasing the operation speed of the input circuit. The address buffer includes a differential amplifier Ai which receives an input signal Ai and outputs a pair of differential signals A-come-first-served latch circuit detects, latches and outputs one of the paired differential signals that has changed first. Activation/inactivation of the differential amplifier is done by turning on and off an N-channel MOS transistor through a Set signal. When activated, the differential amplifier generates a potential difference between the paired differential signals and, when inactivated, has its paired differential signals go low.

Abstract translation: 在诸如地址缓冲器的半导体器件的输入电路中，提供了一种排除了将时序余量从捕获输入信号到其锁存和输出的布置，从而增加了输入电路的操作速度。 地址缓冲器包括差分放大器Ai，其接收输入信号Ai并输出一对差分信号A先来先生的锁存电路检测，锁存和输出首先改变的成对差分信号之一。 差分放大器的激活/失活是通过设置信号来打开和关闭N沟道MOS晶体管来实现的。 当被激活时，差分放大器产生成对的差分信号之间的电位差，当失活时，它的成对差分信号变低。

公开(公告)号：US08791214B2

公开(公告)日：2014-07-29

申请号：US13824821

申请日：2012-05-25

Applicant: Kan Takeuchi ,  Etsuko Suzuki ,  Kunihiro Morinaga ,  Kazuo Arita

Inventor： Kan Takeuchi ,  Etsuko Suzuki ,  Kunihiro Morinaga ,  Kazuo Arita

IPC: B32B15/092 ,  B32B27/04 ,  C08G8/32 ,  C08L61/14 ,  C08L63/00

CPC classification number: H05K3/00 ,  C08G8/32 ,  C08G59/4223 ,  C08G63/133 ,  C08G63/605 ,  C08J5/24 ,  C09D161/14 ,  C09D167/00 ,  H01L23/29 ,  H01L2924/0002 ,  H05K1/0353 ,  Y10T428/2915 ,  Y10T428/31529 ,  Y10T442/2475 ,  C08L63/00 ,  H01L2924/00

Abstract: A low dielectric constant, a low dielectric loss tangent, and heat resistance are achieved. An active ester resin that has a resin structure produced by reacting a polyfunctional phenolic compound (a1) with a monofunctional aromatic carboxylic acid or its chloride (a2) and an aromatic dicarboxylic acid or its chloride (a3). The polyfunctional phenolic compound (a1) is represented by structural formula (1) below: (where Ar represents a benzene ring, a naphthalene ring, a benzene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, or a naphthalene ring nuclear-substituted by an alkyl group having 1 to 4 carbon atoms, X represents a methylene group, a divalent cyclic aliphatic hydrocarbon group, a phenylene dimethylene group, or a biphenylene-dimethylene group, and n represents the number of repeating units and the average thereof is in a range of 0.5 to 10).

Abstract translation: 实现了低介电常数，低介电损耗角正切和耐热性。 具有通过使多官能性酚化合物（a1）与单官能芳族羧酸或其氯化物（a2）和芳香族二羧酸或其氯化物（a3）反应而制造的树脂结构的活性酯树脂。 多官能酚类化合物（a1）由下述结构式（1）表示：（其中Ar表示苯环，萘环，被碳原子数1〜4的烷基核取代的苯环或萘环 被具有1至4个碳原子的烷基核取代，X表示亚甲基，二价环状脂族烃基，亚苯基二亚甲基或亚联苯基 - 二亚甲基，n表示重复单元的数量和平均 在0.5〜10的范围内。

公开(公告)号：US20100203724A1

公开(公告)日：2010-08-12

申请号：US12764411

申请日：2010-04-21

Applicant: Takako FUNAKOSHI ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako FUNAKOSHI ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 公开了一种用于制造具有多层埋置布线的半导体集成电路器件的制造技术，并且防止了在其底部连接到埋地布线的插头与嵌入布线之间的界面处的应力迁移引起的不连续性的发生，以及 埋地线。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US20080303158A1

公开(公告)日：2008-12-11

申请号：US12188591

申请日：2008-08-08

Applicant: Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

Inventor： Takako Funakoshi ,  Eiichi Murakami ,  Kazumasa Yanagisawa ,  Kan Takeuchi ,  Hideo Aoki ,  Hizuru Yamaguchi ,  Takayuki Oshima ,  Kazuyuki Tsunokuni ,  Kousuke Okuyama

IPC: H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/823871 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 μm and is smaller than about 1.44 μm, and the width of a second Cu wiring and the diameter of a plug are about 0.18 μm, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract translation: 在具有多层埋地布线的半导体集成电路器件中，旨在防止在其底部连接到埋地布线的插头与埋地布线之间的界面处的应力迁移引起的不连续性的发生。 例如，在第一Cu布线的宽度不小于约0.9μm且小于约1.44μm的情况下，并且第二Cu布线的宽度和塞子的直径为约0.18μm的情况下，存在 布置两个或更多个将第一布线和第二铜布线彼此电连接的插头。

公开(公告)号：US20050023615A1

公开(公告)日：2005-02-03

申请号：US10929424

申请日：2004-08-31

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L21/8247 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/04 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L27/01 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/036 ,  H01L31/062 ,  H01L31/112 ,  H01L31/113

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract translation: 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。

公开(公告)号：US07309892B2

公开(公告)日：2007-12-18

申请号：US11439152

申请日：2006-05-24

Applicant: Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

Inventor： Kazuo Yano ,  Tomoyuki Ishii ,  Takashi Hashimoto ,  Koichi Seki ,  Masakazu Aoki ,  Takeshi Sakata ,  Yoshinobu Nakagome ,  Kan Takeuchi

IPC: H01L29/76 ,  H01L29/788 ,  H01L29/94

CPC classification number: B82Y10/00 ,  G11C11/22 ,  G11C11/404 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/06 ,  G11C2216/08 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11551 ,  H01L27/1203 ,  H01L29/42328 ,  H01L29/513 ,  H01L29/66825 ,  H01L29/7613 ,  H01L29/785 ,  H01L29/7888

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract translation: 一种场效应半导体元件，其具有较少数量的元件和减小的面积，并能够自身存储数据，而不需要在低温下进行冷却;以及采用该半导体元件的存储器件。 栅极沟道电容被设置得如此小，以致捕获捕获一个电子或空穴是否可以根据半导体FET元件的电流的变化来明确且明显地被检测。 通过检测通过在陷阱中捕获电子或空穴而导致的半导体元件的阈值电压的变化，可以在室温下实现数据存储。