公开(公告)号：US20060081885A1

公开(公告)日：2006-04-20

申请号：US11228269

申请日：2005-10-26

申请人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

发明人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些镀层材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20050095852A1

公开(公告)日：2005-05-05

申请号：US10694793

申请日：2003-10-29

申请人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/745 ,  H01L21/44 ,  H01L29/76

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些电镀材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20060166474A1

公开(公告)日：2006-07-27

申请号：US11050790

申请日：2005-01-27

申请人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

发明人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/20

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20070222066A1

公开(公告)日：2007-09-27

申请号：US11308433

申请日：2006-03-24

申请人： Cyril Cabral ,  Hariklia Deligianni ,  Randolph Knarr ,  Sandra Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe Vereecken

发明人： Cyril Cabral ,  Hariklia Deligianni ,  Randolph Knarr ,  Sandra Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

摘要翻译： 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

公开(公告)号：US20050127518A1

公开(公告)日：2005-06-16

申请号：US11047652

申请日：2005-02-02

申请人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

发明人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

IPC分类号： B32B15/04 ,  C25D3/56 ,  C25D9/08 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

公开(公告)号：US20050104216A1

公开(公告)日：2005-05-19

申请号：US10714966

申请日：2003-11-18

申请人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

发明人： Cyril Cabral ,  Stefanie Chiras ,  Emanuel Cooper ,  Hariklia Deligianni ,  Andrew Kellock ,  Judith Rubino ,  Roger Tsai

IPC分类号： B32B15/04 ,  C25D3/56 ,  C25D9/08 ,  H01L21/288 ,  H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L29/40

CPC分类号： H01L21/2885 ,  C25D9/08 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2224/05007

摘要： A composite material comprising a layer containing copper, and an electrodeposited CoWP film on the copper layer. The CoWP film contains from 11 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a method of making an interconnect structure comprising: providing a trench or via within a dielectric material, and a conducting metal containing copper within the trench or the via; and forming a CoWP film by electrodeposition on the copper layer. The CoWP film contains from 10 atom percent to 25 atom percent phosphorus and has a thickness from 5 nm to 200 nm. The invention is also directed to a interconnect structure comprising a dielectric layer in contact with a metal layer; an electrodeposited CoWP film on the metal layer, and a copper layer on the CoWP film.

摘要翻译： 一种复合材料，其包含含有铜的层和在铜层上的电沉积CoWP膜。 CoWP膜含有11原子％至25原子％的磷并具有5nm至200nm的厚度。 本发明还涉及一种制造互连结构的方法，包括：在介电材料内提供沟槽或通孔，以及在沟槽或通孔内容纳铜的导电金属; 并通过电沉积在铜层上形成CoWP膜。 CoWP膜含有10原子％至25原子％的磷，并且具有5nm至200nm的厚度。 本发明还涉及包括与金属层接触的电介质层的互连结构; 金属层上的电沉积CoWP膜，CoWP膜上的铜层。

公开(公告)号：US20080142894A1

公开(公告)日：2008-06-19

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L27/088 ,  H01L29/423

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20050116230A1

公开(公告)日：2005-06-02

申请号：US10722557

申请日：2003-11-28

申请人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

发明人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

IPC分类号： H01L21/8238 ,  H01L27/108 ,  H01L29/49

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US20060186490A1

公开(公告)日：2006-08-24

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

发明人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

公开(公告)号：US20060264048A1

公开(公告)日：2006-11-23

申请号：US11461220

申请日：2006-07-31

申请人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

发明人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。