公开(公告)号：US20060086616A1

公开(公告)日：2006-04-27

申请号：US11245490

申请日：2005-10-07

申请人： Keiichi Kurashina ,  Mizuki Nagai ,  Satoru Yamamoto ,  Hiroyuki Kanda ,  Koji Mishima ,  Shinya Morisawa ,  Junji Kunisawa ,  Kunihito Ide ,  Hidenao Suzuki ,  Emanuel Cooper ,  Philippe Vereecken ,  Brett Baker-O' Neal ,  Hariklia Deligianni

发明人： Keiichi Kurashina ,  Mizuki Nagai ,  Satoru Yamamoto ,  Hiroyuki Kanda ,  Koji Mishima ,  Shinya Morisawa ,  Junji Kunisawa ,  Kunihito Ide ,  Hidenao Suzuki ,  Emanuel Cooper ,  Philippe Vereecken ,  Brett Baker-O' Neal ,  Hariklia Deligianni

IPC分类号： C25D21/12 ,  C25B15/00

CPC分类号： C25D5/22 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/002 ,  C25D17/004 ,  C25D17/005 ,  C25D17/12 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76877

摘要： A plating apparatus can securely carry out a flattening plating of a substrate to form a plated film having a flat surface without using a costly mechanism, and without applying an extra plating to the substrate. The plating apparatus includes a substrate holder; a cathode section having a seal member for watertightly sealing a peripheral portion of the substrate, and a cathode electrode for supplying an electric current to the substrate; an anode disposed in a position facing the surface of the substrate; a porous member disposed between the anode and the surface of the substrate; a constant-voltage control section for controlling a voltage applied between the cathode electrode and the anode at a constant value; and a current monitor section for monitoring an electric current flowing between the cathode electrode and the anode, and feeding back a detection signal to the constant-voltage control section.

摘要翻译： 电镀装置可以可靠地进行基板的平坦化镀以形成具有平坦表面的镀膜而不使用昂贵的机构，并且不对基板施加额外的电镀。 电镀装置包括：基板支架; 具有用于水密密封基板的周边部分的密封部件的阴极部分和用于向基板供给电流的阴极电极; 设置在面向所述基板的表面的位置的阳极; 设置在所述阳极和所述基板的表面之间的多孔构件; 恒定电压控制部分，用于以恒定值控制在所述阴极和所述阳极之间施加的电压; 以及电流监视部分，用于监视在阴极和阳极之间流动的电流，并将检测信号反馈到恒压控制部分。

公开(公告)号：US20060081885A1

公开(公告)日：2006-04-20

申请号：US11228269

申请日：2005-10-26

申请人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

发明人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些镀层材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20050241946A1

公开(公告)日：2005-11-03

申请号：US11016924

申请日：2004-12-21

申请人： Mizuki Nagai ,  Hiroyuki Kanda ,  Keiichi Kurashina ,  Satoru Yamamoto ,  Ryoichi Kimizuka ,  Hariklia Deligianni ,  Brett Baker ,  Keith Kwietniak ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Mizuki Nagai ,  Hiroyuki Kanda ,  Keiichi Kurashina ,  Satoru Yamamoto ,  Ryoichi Kimizuka ,  Hariklia Deligianni ,  Brett Baker ,  Keith Kwietniak ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： C25D3/38 ,  C25D5/00 ,  C25D5/02 ,  C25D5/08 ,  C25D5/18 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  H01L21/768

CPC分类号： C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  C25D17/008 ,  H01L21/2885 ,  H01L21/76877

摘要： A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

摘要翻译： 电镀方法能够机械地和电化学地优先在诸如沟槽和通孔的精细互连凹槽中沉积镀膜，并将镀膜沉积到更平坦的表面上。 电镀方法包括：设置具有导电层面向阳极的细微互连凹槽的衬底; 在基板和阳极之间设置多孔构件; 在基板和阳极之间填充电镀液; 并且重复保持导电层和多孔构件彼此接触并相对于彼此移动导电层和多孔构件的过程，使导电层和阳极之间的电流通过，同时保持导电 相对于多孔构件的静止层，以及停止在导电层和阳极之间的电流的供给的处理。

公开(公告)号：US20050095852A1

公开(公告)日：2005-05-05

申请号：US10694793

申请日：2003-10-29

申请人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/745 ,  H01L21/44 ,  H01L29/76

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些电镀材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20090095634A1

公开(公告)日：2009-04-16

申请号：US11907589

申请日：2007-10-15

申请人： Natsuki Makino ,  Keisuke Namiki ,  Kunihito Ide ,  Junji Kunisawa ,  Katsuyuki Musaka ,  Philippe Vereecken ,  Brett C. Baker-O'Neal ,  Hariklia Deligianni ,  Keith Kwietniak

发明人： Natsuki Makino ,  Keisuke Namiki ,  Kunihito Ide ,  Junji Kunisawa ,  Katsuyuki Musaka ,  Philippe Vereecken ,  Brett C. Baker-O'Neal ,  Hariklia Deligianni ,  Keith Kwietniak

IPC分类号： C25D5/48 ,  C25D5/00

CPC分类号： C25D17/00 ,  C25D17/008 ,  C25D21/12 ,  H01L21/2885 ,  H01L21/76877

摘要： A plating method can form a plated film having a uniform thickness over the entire surface, including the peripheral surface, of a substrate. The plating method includes: disposing an anode so as to face a conductive film, formed on a substrate, which serves as a cathode, and disposing an auxiliary cathode on an ring-shaped seal member for sealing a peripheral portion of the substrate; bringing the conductive film, the anode and the auxiliary cathode into contact with a plating solution; and supplying electric currents between the anode and the conductive film, and between the anode and the auxiliary cathode to carry out plating.

摘要翻译： 电镀方法可以在基板的整个表面（包括外周表面）上形成均匀厚度的镀膜。 电镀方法包括：将阳极设置成面对形成在用作阴极的基板上的导电膜，并将辅助阴极设置在用于密封基板的周边部分的环形密封构件上; 使导电膜，阳极和辅助阴极与电镀液接触; 并且在阳极和导电膜之间以及阳极和辅助阴极之间提供电流以进行电镀。

公开(公告)号：US20070222066A1

公开(公告)日：2007-09-27

申请号：US11308433

申请日：2006-03-24

申请人： Cyril Cabral ,  Hariklia Deligianni ,  Randolph Knarr ,  Sandra Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe Vereecken

发明人： Cyril Cabral ,  Hariklia Deligianni ,  Randolph Knarr ,  Sandra Malhotra ,  Stephen Rossnagel ,  Xiaoyan Shao ,  Anna Topol ,  Philippe Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

摘要翻译： 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

公开(公告)号：US20060166474A1

公开(公告)日：2006-07-27

申请号：US11050790

申请日：2005-01-27

申请人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

发明人： Philippe Vereecken ,  Veeraraghavan Basker ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Martin Frank ,  Rajarao Jammy ,  Vamsi Paruchuri ,  Katherine Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/20

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20050199502A1

公开(公告)日：2005-09-15

申请号：US11123117

申请日：2005-05-06

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Horkans ,  Keith Kwietniak ,  Michael Lane ,  Sandra Malhotra ,  Fenton McFeely ,  Conal Murray ,  Kenneth Rodbell ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Horkans ,  Keith Kwietniak ,  Michael Lane ,  Sandra Malhotra ,  Fenton McFeely ,  Conal Murray ,  Kenneth Rodbell ,  Philippe Vereecken

IPC分类号： C25D5/18 ,  C25D7/12 ,  C25D5/02

CPC分类号： C25D5/18 ,  C25D7/12 ,  Y10S428/926 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12903

摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

摘要翻译： 导电材料电镀在可镀敷的电阻金属阻挡层上，该层使用任选地包含超填充添加剂和抑制剂的电镀槽，并且通过改变作为电镀金属面积的函数的电流或电压。 还提供了一种结构，其包括衬底，位于衬底上的可镀金属阻挡层和位于可镀电阻金属阻挡层上的导电材料的相对连续的均匀电镀层。

公开(公告)号：US20060076685A1

公开(公告)日：2006-04-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

公开(公告)号：US20050006242A1

公开(公告)日：2005-01-13

申请号：US10615794

申请日：2003-07-10

申请人： Panayotis Andricacos ,  Dean Chung ,  Hariklia Deligianni ,  James Fluegel ,  Keith Kwietniak ,  Peter Locke ,  Darryl Restaino ,  Soon-Cheon Seo ,  Philippe Vereecken ,  Erick Walton

发明人： Panayotis Andricacos ,  Dean Chung ,  Hariklia Deligianni ,  James Fluegel ,  Keith Kwietniak ,  Peter Locke ,  Darryl Restaino ,  Soon-Cheon Seo ,  Philippe Vereecken ,  Erick Walton

IPC分类号： C23C18/16 ,  C25D21/12 ,  C25D21/18

CPC分类号： C23C18/1617 ,  C23C18/1683 ,  C25D21/12 ,  C25D21/18

摘要： An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

摘要翻译： 公开了一种稳定湿化学浴的改进方法。 通常，这种浴用于处理工件的工艺中，例如用于将金属电镀到基底上的电镀工艺。 特别地，本发明涉及镀铜浴。 更具体地说，本发明涉及镀铜浴的稳定性。 更具体地，本发明涉及通过监测铜电镀浴中有害副产物的积累来防止空隙形成。