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37 条记录 (耗时 0.04 秒)

    Field Effect Transistor With Etched-Back Gate Dielectric
    6.
    发明申请
    Field Effect Transistor With Etched-Back Gate Dielectric 审中-公开
    具有蚀刻背栅介质的场效应晶体管

    公开(公告)号：US20060189083A1

    公开(公告)日：2006-08-24

    申请号：US11279659

    申请日：2006-04-13

    申请人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

    发明人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

    IPC分类号： H01L21/8234 ,  H01L23/58

    CPC分类号： H01L21/31111 ,  H01L21/28194 ,  H01L21/31105 ,  H01L21/31122 ,  H01L29/517

    摘要： An ultrathin high-k gate dielectric made for use in a field-effect transistor is provided. The gate dialectric is made by depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching.

    摘要翻译： 提供了一种用于场效晶体管的超薄高k栅极电介质。 栅极方言是通过在衬底上沉积高k栅极电介质材料并通过对高k栅极电介质材料进行稀化处理而形成超薄高k电介质而制成的。 用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。

    Field effect transistor with etched-back gate dielectric
    7.
    发明申请
    Field effect transistor with etched-back gate dielectric 有权
    具有蚀刻背栅电介质的场效应晶体管

    公开(公告)号：US20050127417A1

    公开(公告)日：2005-06-16

    申请号：US10730892

    申请日：2003-12-10

    申请人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

    发明人： Katherine Saenger ,  Rajarao Jammy ,  Vijay Narayanan

    IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L21/314 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/94

    CPC分类号： H01L21/31111 ,  H01L21/28194 ,  H01L21/31105 ,  H01L21/31122 ,  H01L29/517

    摘要： A method for making an ultrathin high-k gate dielectric for use in a field effect transistor is provided. The method involves depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching. In addition to the above, the present invention relates to an ultrathin high-k gate dielectric made for use in a field-effect transistor made by the above method.

    摘要翻译： 提供一种用于制造用于场效应晶体管的超薄高k栅极电介质的方法。 该方法包括在衬底上沉积高k栅极电介质材料，并通过对高k栅极电介质材料进行稀化处理来形成超薄高介电常数。 用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。 除了上述之外，本发明涉及一种用于通过上述方法制造的场效应晶体管的超薄高k栅极电介质。

    FLIP FERAM CELL AND METHOD TO FORM SAME
    9.
    发明申请
    FLIP FERAM CELL AND METHOD TO FORM SAME 有权
    翻转毛细胞及其形成方法

    公开(公告)号：US20070164337A1

    公开(公告)日：2007-07-19

    申请号：US11687000

    申请日：2007-03-16

    申请人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

    发明人： James Adkisson ,  Charles Black ,  Alfred Grill ,  Randy Mann ,  Deborah Neumayer ,  Wilbur Pricer ,  Katherine Saenger ,  Thomas Shaw

    IPC分类号： H01L29/94

    CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L27/11502 ,  H01L27/11507 ,  Y10S438/977

    摘要： A method of forming an integrated ferroelectric/CMOS structure which effectively separates incompatible high temperature deposition and annealing processes is provided. The method of the present invention includes separately forming a CMOS structure and a ferroelectric delivery wafer. These separate structures are then brought into contact with each and the ferroelectric film of the delivery wafer is bonded to the upper conductive electrode layer of the CMOS structure by using a low temperature anneal step. A portion of the delivery wafer is then removed providing an integrated FE/CMOS structure wherein the ferroelectric capacitor is formed on top of the CMOS structure. The capacitor is in contact with the transistor of the CMOS structure through all the wiring levels of the CMOS structure.

    摘要翻译： 提供了一种形成集成的铁电/ CMOS结构的方法，其有效地分离不兼容的高温沉积和退火工艺。 本发明的方法包括分别形成CMOS结构和铁电输送晶片。 然后使这些分离的结构与每个结构接触，并且通过使用低温退火步骤将输送晶片的铁电体膜结合到CMOS结构的上导电电极层。 然后去除输送晶片的一部分，提供集成的FE / CMOS结构，其中铁电电容器形成在CMOS结构的顶部。 电容器通过CMOS结构的所有布线级与CMOS结构的晶体管接触。