公开(公告)号：US20060081885A1

公开(公告)日：2006-04-20

申请号：US11228269

申请日：2005-10-26

申请人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

发明人： Katherine Saenger ,  Cyril Cabral ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Caliopi Andricacos ,  Philippe Vereecken ,  Emanuel Cooper

IPC分类号： H01L29/76 ,  H01L29/745

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些镀层材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20050095852A1

公开(公告)日：2005-05-05

申请号：US10694793

申请日：2003-10-29

申请人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Katherine Saenger ,  Cyril Cabral ,  Emanuel Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L29/745 ,  H01L21/44 ,  H01L29/76

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

摘要翻译： 公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括通过电镀沉积的至少一些材料以及包括至少部分镀覆的金属栅极的FET器件。 还公开了一种用于制造用于FET的金属栅极的方法，其中金属栅极包括至少一些电镀材料，并且该方法包括以下步骤：选择具有顶表面和凹陷区域的衬底; 在衬底上共形沉积导电种子层; 并在种子层上电镀填充栅极金属以填充和覆盖凹陷区域。

公开(公告)号：US20060076685A1

公开(公告)日：2006-04-13

申请号：US11265302

申请日：2005-11-03

申请人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC分类号： H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

公开(公告)号：US20050006242A1

公开(公告)日：2005-01-13

申请号：US10615794

申请日：2003-07-10

申请人： Panayotis Andricacos ,  Dean Chung ,  Hariklia Deligianni ,  James Fluegel ,  Keith Kwietniak ,  Peter Locke ,  Darryl Restaino ,  Soon-Cheon Seo ,  Philippe Vereecken ,  Erick Walton

发明人： Panayotis Andricacos ,  Dean Chung ,  Hariklia Deligianni ,  James Fluegel ,  Keith Kwietniak ,  Peter Locke ,  Darryl Restaino ,  Soon-Cheon Seo ,  Philippe Vereecken ,  Erick Walton

IPC分类号： C23C18/16 ,  C25D21/12 ,  C25D21/18

CPC分类号： C23C18/1617 ,  C23C18/1683 ,  C25D21/12 ,  C25D21/18

摘要： An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.

摘要翻译： 公开了一种稳定湿化学浴的改进方法。 通常，这种浴用于处理工件的工艺中，例如用于将金属电镀到基底上的电镀工艺。 特别地，本发明涉及镀铜浴。 更具体地说，本发明涉及镀铜浴的稳定性。 更具体地，本发明涉及通过监测铜电镀浴中有害副产物的积累来防止空隙形成。

公开(公告)号：US20050241946A1

公开(公告)日：2005-11-03

申请号：US11016924

申请日：2004-12-21

申请人： Mizuki Nagai ,  Hiroyuki Kanda ,  Keiichi Kurashina ,  Satoru Yamamoto ,  Ryoichi Kimizuka ,  Hariklia Deligianni ,  Brett Baker ,  Keith Kwietniak ,  Panayotis Andricacos ,  Philippe Vereecken

发明人： Mizuki Nagai ,  Hiroyuki Kanda ,  Keiichi Kurashina ,  Satoru Yamamoto ,  Ryoichi Kimizuka ,  Hariklia Deligianni ,  Brett Baker ,  Keith Kwietniak ,  Panayotis Andricacos ,  Philippe Vereecken

IPC分类号： C25D3/38 ,  C25D5/00 ,  C25D5/02 ,  C25D5/08 ,  C25D5/18 ,  C25D7/12 ,  C25D17/00 ,  H01L21/288 ,  H01L21/768

CPC分类号： C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/007 ,  C25D17/008 ,  H01L21/2885 ,  H01L21/76877

摘要： A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.

摘要翻译： 电镀方法能够机械地和电化学地优先在诸如沟槽和通孔的精细互连凹槽中沉积镀膜，并将镀膜沉积到更平坦的表面上。 电镀方法包括：设置具有导电层面向阳极的细微互连凹槽的衬底; 在基板和阳极之间设置多孔构件; 在基板和阳极之间填充电镀液; 并且重复保持导电层和多孔构件彼此接触并相对于彼此移动导电层和多孔构件的过程，使导电层和阳极之间的电流通过，同时保持导电 相对于多孔构件的静止层，以及停止在导电层和阳极之间的电流的供给的处理。

公开(公告)号：US20050199502A1

公开(公告)日：2005-09-15

申请号：US11123117

申请日：2005-05-06

申请人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Horkans ,  Keith Kwietniak ,  Michael Lane ,  Sandra Malhotra ,  Fenton McFeely ,  Conal Murray ,  Kenneth Rodbell ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Hariklia Deligianni ,  Wilma Horkans ,  Keith Kwietniak ,  Michael Lane ,  Sandra Malhotra ,  Fenton McFeely ,  Conal Murray ,  Kenneth Rodbell ,  Philippe Vereecken

IPC分类号： C25D5/18 ,  C25D7/12 ,  C25D5/02

CPC分类号： C25D5/18 ,  C25D7/12 ,  Y10S428/926 ,  Y10T428/12493 ,  Y10T428/12528 ,  Y10T428/12771 ,  Y10T428/12778 ,  Y10T428/12903

摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.

摘要翻译： 导电材料电镀在可镀敷的电阻金属阻挡层上，该层使用任选地包含超填充添加剂和抑制剂的电镀槽，并且通过改变作为电镀金属面积的函数的电流或电压。 还提供了一种结构，其包括衬底，位于衬底上的可镀金属阻挡层和位于可镀电阻金属阻挡层上的导电材料的相对连续的均匀电镀层。

公开(公告)号：US06967131B2

公开(公告)日：2005-11-22

申请号：US10694793

申请日：2003-10-29

申请人： Katherine L. Saenger ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe M. Vereecken

发明人： Katherine L. Saenger ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe M. Vereecken

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8283

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

公开(公告)号：US20050001325A1

公开(公告)日：2005-01-06

申请号：US10611931

申请日：2003-07-03

申请人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

发明人： Panayotis Andricacos ,  Shyng-Tsong Chen ,  John Cotte ,  Hariklia Deligianni ,  Mahadevaiyer Krishnan ,  Wei-Tsu Tseng ,  Philippe Vereecken

IPC分类号： H01L21/00 ,  H01L21/288 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/2885 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76874 ,  H01L21/76883

摘要： Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.

摘要翻译： 通过在衬垫材料的存在下使用选择性蚀刻和/或选择性电镀选择性地封盖铜来制造图案化的铜结构。 提供了用于解决在电蚀和/或电镀过程中作为电解质增加的电阻路径从晶片边缘向内流动的问题的装置。

公开(公告)号：US20060163055A1

公开(公告)日：2006-07-27

申请号：US11050899

申请日：2005-01-27

申请人： Philippe Vereecken ,  Panayotis Andricacos ,  Hariklia Deligianni ,  Keith Kwietniak ,  Caliopi Andricacos

发明人： Philippe Vereecken ,  Panayotis Andricacos ,  Hariklia Deligianni ,  Keith Kwietniak ,  Caliopi Andricacos

IPC分类号： C25D21/12

CPC分类号： C25D21/12 ,  H01L21/2885 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

摘要： An apparatus for direct electroplating of a conductive material, such as copper, on resistive liners or substrates is provided. The apparatus includes an integrated in-situ measuring system to follow the actual progress of the front of the conductive material during plating. Feed-back of this information to a power supply allows for more precise control of the effective current density during plating.

摘要翻译： 提供了一种用于在电阻衬片或衬底上直接电镀诸如铜的导电材料的设备。 该装置包括一体化的原位测量系统，以跟踪电镀期间导电材料前部的实际进展。 将该信息反馈给电源允许在电镀期间更有效地控制有效电流密度。

公开(公告)号：US20060283709A1

公开(公告)日：2006-12-21

申请号：US11155495

申请日：2005-06-20

申请人： Panayotis Andricacos ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Caliopo Andricacos

发明人： Panayotis Andricacos ,  Emanuel Cooper ,  John Cotte ,  Hariklia Deligianni ,  Caliopo Andricacos

IPC分类号： C25C7/02

CPC分类号： C25D17/10 ,  C25D11/02 ,  C25D17/12

摘要： Various counter-electrodes for electroplating, electrodeposition or anodizing of substrates are disclosed. According to certain embodiments, multi-segmented counter-electrodes are provided. According to additional embodiments, counter-electrodes having concave or convex top surfaces are provided. The disclosed counter-electrodes enable greater control over electrodeposition, electroetching and anodizing processes for resistive substrates, as well as more uniform plating and etching of resistive substrates. Methods for electroplating, electrodeposition or anodizing of resistive substrates using multi-segmented counter-electrodes are also provided.

摘要翻译： 公开了用于电镀，电沉积或阳极氧化基板的各种对电极。 根据某些实施例，提供多段对置电极。 根据另外的实施例，提供具有凹面或凸面顶面的对电极。 所公开的对电极能够更好地控制电沉积，电蚀和阳极氧化工艺的电阻衬底，以及更均匀的电镀和蚀刻电阻衬底。 还提供了使用多分段对电极的电镀，电沉积或阳极氧化电阻基板的方法。