公开(公告)号：US07060559B2

公开(公告)日：2006-06-13

申请号：US10352083

申请日：2003-01-28

申请人： Yoshio Ozawa ,  Katsuhiko Hieda ,  Atsuko Kawasaki

发明人： Yoshio Ozawa ,  Katsuhiko Hieda ,  Atsuko Kawasaki

IPC分类号： H01L21/336 ,  H01L21/76

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： In a method of manufacturing a semiconductor device having a nonvolatile semiconductor memory element with a two-layered gate structure in which a floating gate and control gate are stacked, a polysilicon layer serving as the floating gate is stacked on a silicon substrate via a tunnel insulating film. Then, the silicon layer, tunnel insulating film, and substrate are selectively etched to form an element isolation trench. A nitride film is formed on the sidewall surface of the silicon layer exposed into the element isolation trench. An oxide film is buried in the element isolation trench. A conductive film serving as the control gate is stacked on the oxide film and silicon layer via an electrode insulating film. The conductive film, electrode insulating film, and silicon layer are selectively etched to form the control gate and floating gate.

摘要翻译： 在制造半导体器件的方法中，该半导体器件具有堆叠浮置栅极和控制栅极的双层栅极结构的非易失性半导体存储元件，用作浮置栅极的多晶硅层通过隧道绝缘层叠在硅衬底上 电影。 然后，选择性地蚀刻硅层，隧道绝缘膜和衬底以形成元件隔离沟槽。 在露出到元件隔离沟槽中的硅层的侧壁表面上形成氮化物膜。 氧化膜被埋在元件隔离槽中。 用作控制栅极的导电膜通过电极绝缘膜堆叠在氧化膜和硅层上。 选择性地蚀刻导电膜，电极绝缘膜和硅层以形成控制栅极和浮动栅极。

公开(公告)号：US20050224863A1

公开(公告)日：2005-10-13

申请号：US11088000

申请日：2005-03-24

申请人： Katsuhiko Hieda ,  Yoshio Ozawa

发明人： Katsuhiko Hieda ,  Yoshio Ozawa

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/092 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11524 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： A semiconductor device includes a semiconductor substrate, first isolation area on the substrate including first and second trenches, first insulating film in the trenches protruding above the surface, with respect to channel width direction, distance between first insulating film on first and second trenches at position higher than the surface being longer than the distance at a position of the surface, and a memory cell having the channel width direction and provided on the substrate including second insulating film on the surface between first and second trenches, control gate above second insulating film, floating gate between control gate and second insulating film, with respect to dimension in the direction, an upper side of floating gate facing control gate being larger than a lower side of floating gate facing second insulating film, and with respect to the direction, displacement of floating gate to first and second trenches being approximately equal.

摘要翻译： 一种半导体器件，包括半导体衬底，所述衬底上的第一隔离区域包括第一和第二沟槽，相对于沟道宽度方向在所述沟槽的上方突出的沟槽中的第一绝缘膜，位于第一和第二沟槽的位置处的第一绝缘膜之间的距离 高于所述表面的距离比所述表面的距离长;以及存储单元，具有所述沟道宽度方向并且设置在所述基板上，所述基板包括第一和第二沟槽之间的表面上的第二绝缘膜，位于第二绝缘膜上方的控制栅极， 控制栅极与第二绝缘膜之间的浮栅，相对于方向尺寸，浮置栅极面对的控制栅极的上侧大于浮置栅极面对第二绝缘膜的下侧，并且相对于方向，位移 第一和第二沟槽的浮动栅极大致相等。

公开(公告)号：US06787827B2

公开(公告)日：2004-09-07

申请号：US10132255

申请日：2002-04-26

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US06403997B1

公开(公告)日：2002-06-11

申请号：US09621450

申请日：2000-07-21

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US06251763B1

公开(公告)日：2001-06-26

申请号：US09106208

申请日：1998-06-29

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L213205

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a position of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底周围的位于第一侧壁绝缘膜的伪栅极图案的位置上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US08637915B2

公开(公告)日：2014-01-28

申请号：US13007258

申请日：2011-01-14

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：USRE44630E1

公开(公告)日：2013-12-10

申请号：US13616208

申请日：2012-09-14

申请人： Tetsuya Kai ,  Ryuji Ohba ,  Yoshio Ozawa

发明人： Tetsuya Kai ,  Ryuji Ohba ,  Yoshio Ozawa

IPC分类号： H01L21/331

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11521 ,  H01L29/42332 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底上的非易失性存储单元，所述非易失性存储单元包括设置在所述半导体衬底的表面上的隧道绝缘膜，所述隧道绝缘膜包括半导体晶粒，所述半导体晶粒包括在 隧道绝缘膜的两端部比隧道绝缘膜的其他部分所包含的半导体晶粒小的晶粒尺寸，隧道绝缘膜上设置的电荷存储层，设置在电荷存储层上的绝缘膜，以及控制 栅电极设置在绝缘膜上。

公开(公告)号：US08604536B2

公开(公告)日：2013-12-10

申请号：US12406841

申请日：2009-03-18

申请人： Katsuyuki Sekine ,  Yoshio Ozawa

发明人： Katsuyuki Sekine ,  Yoshio Ozawa

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

摘要： A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.

摘要翻译： 半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极 设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜 以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

公开(公告)号：US08324679B2

公开(公告)日：2012-12-04

申请号：US13430153

申请日：2012-03-26

申请人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki Ichige ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US20120282773A1

公开(公告)日：2012-11-08

申请号：US13487280

申请日：2012-06-04

申请人： Isao Kamioka ,  Junichi Shiozawa ,  Ryu Kato ,  Yoshio Ozawa

发明人： Isao Kamioka ,  Junichi Shiozawa ,  Ryu Kato ,  Yoshio Ozawa

IPC分类号： H01L21/302

CPC分类号： H01L29/7881 ,  H01L21/76208 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, a method of manufacturing a semiconductor device includes forming a conductive film whose upper surface and side surface are exposed and an insulation film whose upper surface is exposed, on a semiconductor substrate. The method further includes supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the exposed side surface of the conductive film and the exposed upper surface of the insulation film, by applying a predetermined voltage to the semiconductor substrate, thereby performing anisotropic oxidation or anisotropic nitridation of the exposed side surface of the conductive film and the exposed upper surface of the insulation film.

摘要翻译： 在一个实施例中，制造半导体器件的方法包括在半导体衬底上形成其上表面和侧表面被暴露的导电膜和上表面暴露的绝缘膜。 该方法还包括通过施加微波，射频波或电子回旋共振等将由等离子体产生的等离子体中包含的氧化离子或氮化离子供应到导电膜的暴露侧表面和绝缘膜的暴露的上表面 对半导体衬底施加预定的电压，从而进行导电膜的暴露的侧表面和绝缘膜的暴露的上表面的各向异性氧化或各向异性氮化。