公开(公告)号：US06787827B2

公开(公告)日：2004-09-07

申请号：US10132255

申请日：2002-04-26

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US06403997B1

公开(公告)日：2002-06-11

申请号：US09621450

申请日：2000-07-21

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a portion of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底的围绕着具有第一侧壁绝缘膜的伪栅极图案的部分上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US06251763B1

公开(公告)日：2001-06-26

申请号：US09106208

申请日：1998-06-29

申请人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

发明人： Seiji Inumiya ,  Katsuhiko Hieda ,  Tetsuo Matsuda ,  Yoshio Ozawa

IPC分类号： H01L213205

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659

摘要： A method of manufacturing a semiconductor device comprising the steps of forming a dummy film and a dummy gate pattern at a predetermined gate-forming region on a semiconductor substrate, forming a first side wall insulating film on a side wall of the dummy gate pattern, forming an interlayer insulating film on a position of the semiconductor substrate around the dummy gate pattern bearing the first side wall insulating film, forming a groove by removing the dummy gate pattern, removing a portion of dummy film exposed through the groove while leaving a portion of the first side wall insulating film as well as a portion of the dummy film disposed below the portion of the first side wall insulating film, forming a gate insulating film at least on a bottom surface of the groove, and forming a gate electrode on the gate insulating film formed in the groove.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底上的预定栅极形成区域形成虚设膜和伪栅极图案，在虚拟栅极图案的侧壁上形成第一侧壁绝缘膜，形成 在半导体衬底周围的位于第一侧壁绝缘膜的伪栅极图案的位置上的层间绝缘膜，通过去除伪栅极图案形成沟槽，去除通过沟槽暴露的一部分虚拟膜，同时留下一部分 第一侧壁绝缘膜以及设置在第一侧壁绝缘膜的部分下方的虚设膜的一部分，至少在槽的底面上形成栅极绝缘膜，并且在栅极绝缘上形成栅极电极 胶片形成在凹槽中。

公开(公告)号：US20120112308A1

公开(公告)日：2012-05-10

申请号：US13238617

申请日：2011-09-21

申请人： Tetsuo Matsuda ,  Tomomi Imamura

发明人： Tetsuo Matsuda ,  Tomomi Imamura

IPC分类号： H01L25/00 ,  H01L21/66 ,  H01L21/78

CPC分类号： H01L29/7813 ,  H01L22/14 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/7811 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/0615 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/40499 ,  H01L2224/41113 ,  H01L2224/4117 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： According to one embodiment, a semiconductor device includes a device portion, a first electrode portion, a second electrode portion and a protruding portion. The device portion is provided on a substrate. The first electrode portion is provided on the device portion and is electrically contacted with the device portion. The second electrode portion is provided on the device portion separated from the first electrode portion, and electrically contacted with the device portion. The protruding portion is provided on the device portion and protrudes outward from a peripheral portion of the first electrode portion and the second electrode portion.

摘要翻译： 根据一个实施例，半导体器件包括器件部分，第一电极部分，第二电极部分和突出部分。 器件部分设置在衬底上。 第一电极部分设置在器件部分上并与器件部分电接触。 第二电极部分设置在与第一电极部分分离的器件部分上，并与器件部分电接触。 突出部分设置在装置部分上并从第一电极部分和第二电极部分的周边部分向外突出。

公开(公告)号：US07575664B2

公开(公告)日：2009-08-18

申请号：US11135328

申请日：2005-05-24

申请人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

发明人： Tetsuo Matsuda ,  Hisashi Kaneko ,  Katsuya Okumura

IPC分类号： C25D21/12

CPC分类号： C25D5/16 ,  C25D5/02 ,  C25D5/06 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  H01L21/2885 ,  H01L21/76877 ,  H05K3/423

摘要： A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.

摘要翻译： 对形成在具有凹陷图案的基板上的导电层施加阴极电位。 将与阳极电接触的电镀溶液供给到导电层，以在导电层上形成镀膜。 此时，通过使包含电镀液的浸渍部件面对导电层而供给电镀液。 由于电镀溶液滞留在凹陷中，所以与基板的上表面相比，供给电镀液的量较多，因此抑制了镀膜的镀覆速度。 因此，可以在诸如凹槽或孔的凹陷中优先地形成镀膜。

公开(公告)号：US20080251385A1

公开(公告)日：2008-10-16

申请号：US12116562

申请日：2008-05-07

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D21/12

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有基板保持部分36，其水平地保持并旋转基板，其表面被面向上。 密封材料90接触表面的周缘部分，以水密的方式密封该部分。 阴极电极88在与基板接触时通过电流。 阴极部38与基板保持部36一体旋转。 电极臂部分30在阴极部分38的上方并且可水平和垂直地移动，并且阳极98面向下。 将电镀液注入被镀表面与接近待镀表面的阳极98之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元进行。

公开(公告)号：US06998342B2

公开(公告)日：2006-02-14

申请号：US10835319

申请日：2004-04-30

申请人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

发明人： Tetsuo Matsuda ,  Hiroshi Toyoda ,  Hisashi Kaneko

IPC分类号： H01L21/44

CPC分类号： H01L21/76874 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/405 ,  C23C18/54 ,  C23C28/00 ,  C25D7/123 ,  H01L21/2855 ,  H01L21/288 ,  H01L21/76867 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronic device manufacturing method comprises forming an insulating film above a substrate, forming a to-be-filled region which includes at least one of an interconnection groove and a hole in the insulating film, forming a first conductive film containing a catalyst metal which accelerates electroless plating, so as to line an internal surface of the to-be-filled region, forming a second conductive film on the first conductive film by the electroless plating, so as to line the internal surface of the to-be-filled region via the first conductive film, and forming a third conductive film on the second conductive film by electroplating, so as to fill the to-be-filled region via the first conductive film and the second conductive film.

公开(公告)号：US06632335B2

公开(公告)日：2003-10-14

申请号：US09742110

申请日：2000-12-22

申请人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

发明人： Junji Kunisawa ,  Mitsuko Odagaki ,  Natsuki Makino ,  Koji Mishima ,  Kenji Nakamura ,  Hiroaki Inoue ,  Norio Kimura ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Nobuo Hayasaka ,  Katsuya Okumura ,  Manabu Tsujimura ,  Toshiyuki Morita

IPC分类号： C25D2112

CPC分类号： H01L21/6719 ,  C25D7/123 ,  C25D17/001 ,  C25D17/12 ,  C25D17/14 ,  H01L21/2885 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/6723 ,  H01L21/76877 ,  H01L21/76879 ,  H01L2924/0002 ,  H05K3/423 ,  H01L2924/00

摘要： A plating method and apparatus for a substrate fills a metal, e.g., copper, into a fine interconnection pattern formed in a semiconductor substrate. The apparatus has a substrate holding portion 36 horizontally holding and rotating a substrate with its surface to be plated facing upward. A seal material 90 contacts a peripheral edge portion of the surface, sealing the portion in a watertight manner. A cathode electrode 88 passes an electric current upon contact with the substrate. A cathode portion 38 rotates integrally with the substrate holding portion 36. An electrode arm portion 30 is above the cathode portion 38 and movable horizontally and vertically and has an anode 98 face-down. Plating liquid is poured into a space between the surface to be plated and the anode 98 brought close to the surface to be plated. Thus, plating treatment and treatments incidental thereto can be performed by a single unit.

摘要翻译： 用于衬底的电镀方法和装置将诸如铜的金属填充到形成在半导体衬底中的精细互连图案中。 该装置具有将待镀表面向上水平保持并旋转的衬底的衬底保持部分 36 。 密封材料 90 接触表面的外围边缘部分，以水密的方式密封该部分。 当与基板接触时，阴极电极 88 通过电流。 阴极部分 38 与衬底保持部分 36 整体旋转。 电极臂部分 30 在阴极部分 38 之上，水平和垂直移动并具有阳极 PDAT> 98 面朝下。 将电镀液倒入要被镀表面和靠近待镀表面的阳极 98 之间的空间中。 因此，电镀处理和附带的处理可以通过单个单元执行

公开(公告)号：US06579785B2

公开(公告)日：2003-06-17

申请号：US09767724

申请日：2001-01-24

申请人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

发明人： Hiroshi Toyoda ,  Tetsuo Matsuda ,  Hisashi Kaneko ,  Hideaki Hirabayashi

IPC分类号： H01L2144

CPC分类号： H01L21/76849 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device, which comprises the steps of forming an intermediate layer on an insulating layer, forming a groove in the intermediate layer and the insulating layer, forming a first barrier layer on the intermediate layer, depositing a wiring layer on the first barrier layer to thereby fill the groove with the wiring layer, performing a flattening treatment of the wiring layer, removing a surface portion of the wiring to thereby permit the surface of the wiring to be recessed lower than a surface of the insulating layer, thus forming a recessed portion, forming a second barrier layer on the intermediate layer and on an inner wall of the recessed portion, performing a flattening treatment of the second barrier layer, thereby, and selectively removing the intermediate layer, exposing the insulating layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在绝缘层上形成中间层，在中间层中形成沟槽和绝缘层，在中间层上形成第一阻挡层，在其上沉积布线层 第一阻挡层，从而使布线层填充沟槽，对布线层进行平坦化处理，去除布线的表面部分，从而允许布线的表面比绝缘层的表面凹陷，因此 形成凹部，在所述中间层和所述凹部的内壁上形成第二阻挡层，对所述第二阻挡层进行平坦化处理，从而选择性地除去所述中间层，使所述绝缘层露出。

公开(公告)号：US06518177B1

公开(公告)日：2003-02-11

申请号：US09783561

申请日：2001-02-15

申请人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

发明人： Takashi Kawanoue ,  Junichi Wada ,  Tetsuo Matsuda ,  Hisashi Kaneko

IPC分类号： H01L214763

CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is formed by a compound film &agr;&ggr;x made of at least one element &agr; selected from metal elements and at least one element &ggr; selected from the group consisting of boron, carbon, and nitrogen on a base layer containing oxygen (O), and forming a compound film &agr;&ggr;yOz by causing the compound film &agr;&ggr;x to reduce the base layer and thereby oxidizing the compound film &agr;&ggr;x on an interface of the compound film &agr;&ggr;x and the base layer, wherein each of x and y is a ratio of the number of atoms of the element &ggr; to the number of atoms of the element &agr;, and z is a ratio of the number of atoms of the oxygen to the number of atoms of the element &agr;.

摘要翻译： 通过由选自金属元素的至少一种元素α和在含氧（O）的基底层上选自硼，碳和氮的至少一种元素γ制成的化合物膜，形成半导体器件，以及 通过使化合物膜alphagammax减少基底层从而氧化化合物膜的碱性和底层的界面上的化合物膜，形成化合物膜alphagammayOz，其中x和y分别为原子数 元素γ与元素α的原子数之比，z是氧原子数与元素α原子数之比。