公开(公告)号：US20120196398A1

公开(公告)日：2012-08-02

申请号：US13446621

申请日：2012-04-13

申请人： Katsushi AKITA ,  Takashi ISHIZUKA ,  Kei FUJII ,  Youichi NAGAI ,  Hideaki NAKAHATA

发明人： Katsushi AKITA ,  Takashi ISHIZUKA ,  Kei FUJII ,  Youichi NAGAI ,  Hideaki NAKAHATA

IPC分类号： H01L31/18

CPC分类号： H01L27/14694 ,  B82Y20/00 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/2258 ,  H01L31/035236 ,  H01L31/109 ,  H01L31/1844

摘要： Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.

摘要翻译： 提供一种光电二极管阵列及其制造方法，其保持形成在III-V族半导体衬底上的吸收层的结晶质量，以获得优异的特性，并提高窗口层表面的结晶度; 用于制造光电二极管阵列的外延晶片; 以及制造外延晶片的方法。 制造具有多个吸收区域21的光电二极管阵列1的方​​法包括以下步骤：在n型InP衬底3上生长吸收层7; 在吸收层7上生长InP窗口层; 并且在窗层11中对应于多个吸收区域21的区域中扩散p型杂质。窗口层11通过仅使用金属有机源的MOVPE生长，生长温度等于或低于 的吸收层7。

公开(公告)号：US20110101306A1

公开(公告)日：2011-05-05

申请号：US12916150

申请日：2010-10-29

申请人： Katsushi AKITA ,  Takashi ISHIZUKA ,  Kei FUJII ,  Youichi NAGAI ,  Hideaki NAKAHATA

发明人： Katsushi AKITA ,  Takashi ISHIZUKA ,  Kei FUJII ,  Youichi NAGAI ,  Hideaki NAKAHATA

IPC分类号： H01L31/101 ,  H01L31/18 ,  H01L31/109 ,  H01L27/146

CPC分类号： H01L27/14694 ,  B82Y20/00 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/2258 ,  H01L31/035236 ,  H01L31/109 ,  H01L31/1844

摘要： Provided are a photodiode array and its manufacturing method, which maintain the crystalline quality of an absorption layer formed on a group III-V semiconductor substrate to obtain excellent characteristics, and which improve the crystallinity at the surface of a window layer; an epitaxial wafer used for manufacturing the photodiode array; and a method for manufacturing the epitaxial wafer. A method for manufacturing a photodiode array 1 having a plurality of absorption regions 21, includes the steps of: growing an absorption layer 7 on an n-type InP substrate 3; growing an InP window layer on the absorption layer 7; and diffusing a p-type impurity in regions, in the window layer 11, corresponding to the plurality of absorption regions 21. The window layer 11 is grown by MOVPE using only metal-organic sources, at a growth temperature equal to or lower than that of the absorption layer 7.

摘要翻译： 提供一种光电二极管阵列及其制造方法，其保持形成在III-V族半导体衬底上的吸收层的结晶质量，以获得优异的特性，并提高窗口层表面的结晶度; 用于制造光电二极管阵列的外延晶片; 以及制造外延晶片的方法。 制造具有多个吸收区域21的光电二极管阵列1的方​​法包括以下步骤：在n型InP衬底3上生长吸收层7; 在吸收层7上生长InP窗口层; 并且在窗层11中对应于多个吸收区域21的区域中扩散p型杂质。窗口层11通过仅使用金属有机源的MOVPE生长，生长温度等于或低于 的吸收层7。

公开(公告)号：US20110049573A1

公开(公告)日：2011-03-03

申请号：US12732775

申请日：2010-03-26

申请人： Shin HASHIMOTO ,  Tatsuya TANABE ,  Katsushi AKITA ,  Hideaki NAKAHATA ,  Hiroshi AMANO

发明人： Shin HASHIMOTO ,  Tatsuya TANABE ,  Katsushi AKITA ,  Hideaki NAKAHATA ,  Hiroshi AMANO

IPC分类号： H01L29/205

CPC分类号： H01L29/7787 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/66462 ,  H01L29/872

摘要： A group III nitride semiconductor device and a group III nitride semiconductor wafer are provided. The group III nitride semiconductor device has a channel layer comprising group III nitride-based semiconductor containing Al. The group III nitride semiconductor device can enhance the mobility of the two-dimensional electron gas and improve current characteristics. The group III nitride semiconductor wafer is used to make the group III nitride semiconductor device. The group III nitride semiconductor wafer comprises a substrate made of AlXGa1−XN (0

摘要翻译： 提供III族氮化物半导体器件和III族氮化物半导体晶片。 III族氮化物半导体器件具有包含含有Al的III族氮化物基半导体的沟道层。 III族氮化物半导体器件可以增强二维电子气的迁移率并改善电流特性。 III族氮化物半导体晶片用于制造III族氮化物半导体器件。 III族氮化物半导体晶片包括由Al x Ga 1-x N（0

公开(公告)号：US20120164058A1

公开(公告)日：2012-06-28

申请号：US13402131

申请日：2012-02-22

申请人： Tomoki UEMURA ,  Takashi SAKURADA ,  Shinsuke FUJIWARA ,  Takuji OKAHISA ,  Koji UEMATSU ,  Hideaki NAKAHATA

发明人： Tomoki UEMURA ,  Takashi SAKURADA ,  Shinsuke FUJIWARA ,  Takuji OKAHISA ,  Koji UEMATSU ,  Hideaki NAKAHATA

IPC分类号： C01B21/06 ,  C30B19/12 ,  C30B23/02

CPC分类号： H01L21/02623 ,  C30B25/186 ,  C30B25/20 ,  C30B29/406 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02658

摘要： There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.

摘要翻译： 提供了通过使用包括位错集中区域或反极性区域的氮化镓衬底生长氮化镓晶体来制造在切片的研磨期间具有低位错密度，高结晶度和耐龟裂性的氮化镓晶体的方法， 晶种基片。 在高于1100℃并且等于或低于1300℃的生长温度下生长氮化镓晶体79，以便掩埋位错集中区域或反极性区域17a减少从位错集中区域遗留的位错或 反转区域17a，从而防止在位错集中区域或反极性区域17a上发生新的位错。 这也增加了氮化镓晶体79的结晶度及其在抛光过程中的抗开裂性。

公开(公告)号：US20100314625A1

公开(公告)日：2010-12-16

申请号：US12797617

申请日：2010-06-10

申请人： Hideaki NAKAHATA ,  Shinsuke FUJIWARA ,  Takashi SAKURADA ,  Yoshiyuki YAMAMOTO ,  Seiji NAKAHATA ,  Tomoki UEMURA

发明人： Hideaki NAKAHATA ,  Shinsuke FUJIWARA ,  Takashi SAKURADA ,  Yoshiyuki YAMAMOTO ,  Seiji NAKAHATA ,  Tomoki UEMURA

IPC分类号： H01L29/20 ,  H01L21/20 ,  C01B21/06 ,  C30B23/00

CPC分类号： H01L29/872 ,  C30B25/00 ,  C30B29/406 ,  H01L21/02008 ,  H01L21/0237 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205

摘要： Affords a GaN single-crystal mass, a method of its manufacture, and a semiconductor device and method of its manufacture, whereby when the GaN single-crystal mass is being grown, and when the grown GaN single-crystal mass is being processed into a substrate or like form, as well as when an at least single-lamina semiconductor layer is being formed onto a single-crystal GaN mass in substrate form to manufacture semiconductor devices, cracking is controlled to a minimum. The GaN single-crystal mass 10 has a wurtzitic crystalline structure and, at 30° C., its elastic constant C11 is from 348 GPa to 365 GPa and its elastic constant C13 is from 90 GPa to 98 GPa; alternatively its elastic constant C11 is from 352 GPa to 362 GPa.

摘要翻译： 提供GaN单晶体，其制造方法以及其制造的半导体器件及其制造方法，由此当生长GaN单晶质量时，并且当将生长的GaN单晶体块加工成 衬底或类似形式，以及当至少单层GaN半导体层以衬底形式形成在单晶GaN块上以制造半导体器件时，将裂纹控制到最小。 GaN单晶块10具有纤锌矿结晶结构，在30℃下，其弹性常数C11为348GPa至365GPa，其弹性常数C13为90GPa至98GPa; 或者其弹性常数C11为352GPa至362GPa。