公开(公告)号：US20090134446A1

公开(公告)日：2009-05-28

申请号：US12275995

申请日：2008-11-21

申请人： Katsuyuki SEKINE ,  Yoshio OZAWA ,  Hiroaki TSUNODA

发明人： Katsuyuki SEKINE ,  Yoshio OZAWA ,  Hiroaki TSUNODA

IPC分类号： H01L29/788 ,  H01L29/68 ,  H01L29/66

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/511

摘要： A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the inter-electrode insulating film includes a main insulating film and a plurality of nano-particles in the main insulating film.

摘要翻译： 半导体器件包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的浮栅电极，形成在浮栅电极上的电极间绝缘膜，以及形成在电极间绝缘层上的控制栅电极 膜，其中所述电极间绝缘膜包括主绝缘膜和所述主绝缘膜中的多个纳米颗粒。

公开(公告)号：US20100213534A1

公开(公告)日：2010-08-26

申请号：US12709154

申请日：2010-02-19

申请人： Katsuyuki SEKINE ,  Katsuaki Natori ,  Tetsuya Kai ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Katsuaki Natori ,  Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/40114 ,  H01L29/42336

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films.

摘要翻译： 在设置有存储单元晶体管的非易失性半导体存储器件中，每个存储单元晶体管分别具有隧道绝缘膜，浮栅电极，电极间绝缘膜和元件隔离绝缘膜。 隧道绝缘膜上的浮栅电极设置有从底部顺序形成的第一浮栅电极和第二浮栅电极，第二浮栅电极在沟道宽度方向比第一浮栅电极和第一浮栅电极窄。 元件隔离绝缘膜和第一浮栅电极的上表面的电平相同。 电极间绝缘膜连续地覆盖浮置栅电极的上表面和元件隔离绝缘膜的上表面，并且在与栅极电极的边界部分的氮浓度相比高于边界部分 元件隔离绝缘膜。

公开(公告)号：US20090184365A1

公开(公告)日：2009-07-23

申请号：US12352673

申请日：2009-01-13

申请人： Katsuyuki SEKINE ,  Masaru Kito ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Masaru Kito ,  Yoshio Ozawa

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L27/1203 ,  H01L29/40117 ,  H01L29/4234

摘要： A semiconductor memory device includes a tunnel insulating film, charge storage layer, block insulating film and control gate electrode stacked and formed on the surface of a semiconductor substrate. The charge storage layer is formed of an insulating film containing nitrogen. A dopant that reduces the trap density of charges moved in and out of an internal portion of the charge storage layer via the tunnel insulating film is doped into a region of the charge storage layer on the interface side with the tunnel insulating film or a dopant is doped into the above region with higher concentration in comparison with that of another region.

摘要翻译： 半导体存储器件包括层叠并形成在半导体衬底的表面上的隧道绝缘膜，电荷存储层，块绝缘膜和控制栅电极。 电荷存储层由含氮的绝缘膜形成。 通过隧道绝缘膜将电荷存储层的内部部分移入和移出的电荷的陷阱密度降低的掺杂剂掺杂到与隧道绝缘膜或掺杂剂的界面侧的电荷存储层的区域中 与其他区域相比，掺杂到上述区域中的浓度更高。

公开(公告)号：US20110175157A1

公开(公告)日：2011-07-21

申请号：US13008469

申请日：2011-01-18

申请人： Katsuyuki SEKINE ,  Tetsuya Kai ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/66833 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer; first and second insulating layers; a functional layer; first and second gate electrodes. The first insulating layer opposes the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first insulating layer. The functional layer is provided between the first and second insulating layers. The second gate electrode is separated from the first gate electrode. The first insulating layer is disposed between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer. The charge storabilities in first and second regions of the functional layer are different from that of a third region of the functional layer. The first and second regions oppose the first and second gate electrodes, respectively. The third region is between the first and the second regions.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体层; 第一和第二绝缘层; 功能层; 第一和第二栅电极。 第一绝缘层与半导体层相对。 第二绝缘层设置在半导体层和第一绝缘层之间。 功能层设置在第一和第二绝缘层之间。 第二栅电极与第一栅电极分离。 第一绝缘层设置在第一栅电极和半导体层之间以及第二栅电极和半导体层之间。 功能层的第一和第二区域中的电荷存储能力与功能层的第三区域的电荷存储能力不同。 第一和第二区域分别与第一和第二栅电极相对。 第三区域在第一和第二区域之间。

公开(公告)号：US20090261403A1

公开(公告)日：2009-10-22

申请号：US12406841

申请日：2009-03-18

申请人： Katsuyuki SEKINE ,  Yoshio OZAWA

发明人： Katsuyuki SEKINE ,  Yoshio OZAWA

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

摘要： A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.

摘要翻译： 半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极 设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜 以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

公开(公告)号：US20110175048A1

公开(公告)日：2011-07-21

申请号：US13004287

申请日：2011-01-11

申请人： Katsuyuki SEKINE ,  Ryota FUJITSUKA ,  Yoshio OZAWA

发明人： Katsuyuki SEKINE ,  Ryota FUJITSUKA ,  Yoshio OZAWA

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L45/1273 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16

摘要： According to one embodiment, a nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major face and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face. The corner part has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that the second major surface.

摘要翻译： 根据一个实施例，非易失性存储器件包括第一和第二导电层，电阻变化层和整流元件。 第一导电层具有第一和第二主表面。 第二导电层具有第三和第四主表面，侧面和拐角部分。 第三主表面面向第一主表面并且包括平行于第一主面的平面，并且设置在第四主表面和第一主表面之间。 角部设置在第三主表面和侧面之间。 角部具有高于第三主表面的曲率。 电阻变化层设置在第一和第二导电层之间。 整流元件面向第一导电层的第二主表面。 第三主表面的面积小于第二主表面的面积。

公开(公告)号：US20110069530A1

公开(公告)日：2011-03-24

申请号：US12823467

申请日：2010-06-25

申请人： Katsuyuki SEKINE ,  Ryota Fujitsuka ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Ryota Fujitsuka ,  Yoshio Ozawa

IPC分类号： G11C11/00 ,  H01L21/66

CPC分类号： G11C13/0069 ,  G11C11/005 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/101

摘要： According to one embodiment, there is provided a method of manufacturing a nonvolatile memory device. In this method, a first voltage may be applied to a variable resistive element having a resistance value which is electrically rewritable in a high resistance and in a low resistance. In this method, a second voltage may be applied to the variable resistive element in a case where the resistance value of the variable resistive element to which the first voltage has been applied is greater than a resistance value of the low resistance and is not greater than a resistance value of the high resistance. Further, in this method, the applying of the second voltage to the variable resistive element may be repeated until the resistance value of the variable resistive element to which the second voltage has been applied falls within a range of the resistance value of the low resistance.

摘要翻译： 根据一个实施例，提供了一种制造非易失性存储器件的方法。 在该方法中，可以将第一电压施加到具有电阻可变的电阻值的高电阻和低电阻的可变电阻元件。 在该方法中，在施加了第一电压的可变电阻元件的电阻值大于低电阻的电阻值的情况下，可以向可变电阻元件施加第二电压，并且不大于 电阻值为高电阻。 此外，在该方法中，可以重复向可变电阻元件施加第二电压，直到施加了第二电压的可变电阻元件的电阻值落在低电阻的电阻值的范围内。

公开(公告)号：US20100237402A1

公开(公告)日：2010-09-23

申请号：US12726952

申请日：2010-03-18

申请人： Katsuyuki SEKINE ,  Kensuke TAKANO ,  Masaaki HIGUCHI ,  Tetsuya KAI ,  Yoshio OZAWA

发明人： Katsuyuki SEKINE ,  Kensuke TAKANO ,  Masaaki HIGUCHI ,  Tetsuya KAI ,  Yoshio OZAWA

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.

摘要翻译： 第一选择晶体管形成在半导体衬底上。 存储单元晶体管堆叠在第一选择晶体管上并串联连接。 在存储单元晶体管上形成第二选择晶体管。 存储单元晶体管包括从第一选择晶体管朝向第二选择晶体管的直径增加的锥形半导体柱，形成在半导体柱的侧表面上的隧道电介质膜，形成在半导体柱的侧表面上的电荷存储层 隧道电介质膜，并且其从第一选择晶体管侧朝向第二选择晶体管侧的电荷陷阱密度增加，形成在电荷存储层的侧表面上的块状电介质膜和形成在电荷存储层的侧表面上的导体膜 该块介质膜并用作栅电极。

公开(公告)号：US20090273021A1

公开(公告)日：2009-11-05

申请号：US12432453

申请日：2009-04-29

申请人： Katsuyuki SEKINE ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Yoshio Ozawa ,  Katsuaki Natori ,  Takashi Nakao

发明人： Katsuyuki SEKINE ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Yoshio Ozawa ,  Katsuaki Natori ,  Takashi Nakao

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/4234 ,  H01L29/7887

摘要： A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality of layers including first and second charge storage layers, the second charge storage layer being provided on a nearest side of the block insulating film, the first charge storage layer being provided between the tunnel insulating film and the second charge storage layer, the second charge storage layer having a higher trap density than the first charge storage layer, the second charge storage layer having a smaller band gap than the first charge storage layer, and the second charge storage layer having a higher permittivity than the first charge storage layer and a silicon nitride film.

摘要翻译： 半导体器件包括半导体衬底，半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷存储层，电荷存储层上的块绝缘膜和块绝缘膜上的控制栅电极，电荷 存储层，包括包括第一和第二电荷存储层的多个层，所述第二电荷存储层设置在所述块绝缘膜的最近侧，所述第一电荷存储层设置在所述隧道绝缘膜和所述第二电荷存储层之间 所述第二电荷存储层具有比所述第一电荷存储层高的陷阱密度，所述第二电荷存储层具有比所述第一电荷存储层更小的带隙，并且所述第二电荷存储层具有比所述第一电荷存储层高的介电常数 层和氮化硅膜。

公开(公告)号：US20110068312A1

公开(公告)日：2011-03-24

申请号：US12795197

申请日：2010-06-07

申请人： Katsuyuki SEKINE ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Yoshio Ozawa

IPC分类号： H01L45/00 ,  H01L29/22

CPC分类号： H01L27/2418 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/72 ,  H01L27/1021 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： According to one embodiment, a nonvolatile memory device comprises a plurality of first lines, a plurality of second lines, and memory cells. Each of the memory cells comprise a variable resistor, and a diode. The variable resistor includes a first metal oxide film and is configured to reversibly change resistance value by energy application. The diode includes a second metal oxide film and is connected in series to the variable resistor. The first metal oxide film has at least one of dielectric constant lower than that of the second metal oxide film and physical film thickness greater than that of the second metal oxide film.

摘要翻译： 根据一个实施例，非易失性存储器件包括多个第一线，多条第二线和存储单元。 每个存储单元包括可变电阻器和二极管。 可变电阻器包括第一金属氧化物膜，并且被配置为通过能量施加可逆地改变电阻值。 二极管包括第二金属氧化物膜并串联连接到可变电阻器。 第一金属氧化物膜具有比第二金属氧化物膜低的介电常数中的至少一种，并且物理膜厚度大于第二金属氧化物膜的介电常数。