公开(公告)号：US06509531B2

公开(公告)日：2003-01-21

申请号：US09784904

申请日：2001-02-16

申请人： Norio Sakai ,  Isao Kato ,  Kazuhiro Isebo

发明人： Norio Sakai ,  Isao Kato ,  Kazuhiro Isebo

IPC分类号： H05K111

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/85399 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/4053 ,  H05K3/4611 ,  H05K3/4629 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00012

摘要： A monolithic electronic component includes a composite body having a plurality of stacked ceramic layers. The ceramic layers include interconnecting conductors provided in each of the ceramic layers, including first terminals, arranged on a first end surface in the stacking direction of the composite body, for defining connections with an interconnection substrate, and second terminals, arranged on a second end surface opposite of the first end surface of the composite, for defining connections with a mounted component. The first terminals are defined by conductor layers provided on the first end surface and the second terminals are defined by exposed end surfaces of terminal via-hole conductors which extend from the inner portion of the composite to the second end surface. The exposed end surfaces of the terminal via-hole conductors are flat and are on substantially the same plane as the second end surface.

公开(公告)号：US08012287B2

公开(公告)日：2011-09-06

申请号：US12559589

申请日：2009-09-15

申请人： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

发明人： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

IPC分类号： B32B15/00

CPC分类号： H05K3/4061 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H05K1/0306 ,  H05K3/1266 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0143 ,  H05K2203/0156 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1545 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T156/10 ,  Y10T156/109

摘要： A via hole forming method and a multilayered board manufacturing method improve manufacturing yield by reducing the required processes. The via hole forming method includes a first step of forming a toner image by attaching toner particles, containing a conductive material and having a protruding portion, onto the surface of a first photosensitive member so that the protruding portion is directed to the outside; and a second step of opposing the surface of the first photosensitive member to one principal surface of a green sheet containing an insulating material and transferring the toner image to the one principal surface of the green sheet so that the protruding portions of the toner particles protrude into the green sheet so as to reach the other principal surface of the green sheet and the toner particles are buried in the green sheet. The via holes are formed using an electrophotographic printing method.

摘要翻译： 通孔形成方法和多层板制造方法通过减少所需的工艺来提高制造成品率。 通孔形成方法包括：第一步骤，通过将包含导电材料并具有突出部分的调色剂颗粒附着到第一感光构件的表面上以使得突出部分被引导到外部来形成调色剂图像; 以及将第一感光构件的表面相对于包含绝缘材料的生片的一个主表面并将调色剂图像转印到生片的一个主表面的第二步骤，使得调色剂颗粒的突出部分突出到 生片从而到达生片的另一个主表面和调色剂颗粒被埋在生片中。 通孔使用电子照相印刷法形成。

公开(公告)号：US08308887B2

公开(公告)日：2012-11-13

申请号：US13182465

申请日：2011-07-14

申请人： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

发明人： Kazuhiro Isebo ,  Norio Sakai ,  Kenji Kawakami ,  Nobuaki Ogawa

IPC分类号： B44C1/17 ,  B44C1/165 ,  C03B29/00 ,  B29C65/00 ,  B23P19/00

CPC分类号： H05K3/4061 ,  G03G15/224 ,  G03G15/225 ,  G03G15/6585 ,  G03G15/6591 ,  H05K1/0306 ,  H05K3/1266 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2203/0143 ,  H05K2203/0156 ,  H05K2203/0517 ,  H05K2203/1189 ,  H05K2203/1545 ,  Y10T29/5313 ,  Y10T29/5317 ,  Y10T156/10 ,  Y10T156/109

摘要： A via hole forming method and a multilayered board manufacturing method improve manufacturing yield by reducing the required processes. The via hole forming method includes a first step of forming a toner image by attaching toner particles, containing a conductive material and having a protruding portion, onto the surface of a first photosensitive member so that the protruding portion is directed to the outside; and a second step of opposing the surface of the first photosensitive member to one principal surface of a green sheet containing an insulating material and transferring the toner image to the one principal surface of the green sheet so that the protruding portions of the toner particles protrude into the green sheet so as to reach the other principal surface of the green sheet and the toner particles are buried in the green sheet. The via holes are formed using an electrophotographic printing method.

摘要翻译： 通孔形成方法和多层板制造方法通过减少所需的工艺来提高制造成品率。 通孔形成方法包括：第一步骤，通过将包含导电材料并具有突出部分的调色剂颗粒附着到第一感光构件的表面上以使得突出部分被引导到外部来形成调色剂图像; 以及将第一感光构件的表面相对于包含绝缘材料的生片的一个主表面并将调色剂图像转印到生片的一个主表面的第二步骤，使得调色剂颗粒的突出部分突出到 生片从而到达生片的另一个主表面和调色剂颗粒被埋在生片中。 通孔使用电子照相印刷法形成。

公开(公告)号：US07745734B2

公开(公告)日：2010-06-29

申请号：US11738637

申请日：2007-04-23

申请人： Kazuhiro Isebo

发明人： Kazuhiro Isebo

IPC分类号： H05K1/03

CPC分类号： H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0271 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/183 ,  H05K2201/09481 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A ceramic multilayer substrate includes a plurality of laminated ceramic layers and at least one conductor pattern and disposed on at least one of the ceramic layers. The ceramic multilayer substrate has a cavity in at least a first main surface. The ceramic multilayer substrate includes a deformation preventing pattern disposed on at least one of the ceramic layers having an opening forming the cavity. The deformation preventing pattern surrounds the entire perimeter of the opening and is made of the same material as the conductor pattern.

摘要翻译： 陶瓷多层基板包括多个层压陶瓷层和至少一个导体图案，并设置在至少一个陶瓷层上。 陶瓷多层基板在至少第一主表面中具有空腔。 陶瓷多层基板包括设置在具有形成空腔的开口的至少一个陶瓷层上的变形防止图案。 变形防止图案围绕开口的整个周边并且由与导体图案相同的材料制成。

公开(公告)号：US06860006B2

公开(公告)日：2005-03-01

申请号：US10242424

申请日：2002-09-13

申请人： Norio Sakai ,  Isao Kato ,  Kazuhiro Isebo

发明人： Norio Sakai ,  Isao Kato ,  Kazuhiro Isebo

IPC分类号： H05K3/46 ,  H01L23/12 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H01K3/10

CPC分类号： H01L23/49822 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/85399 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/4053 ,  H05K3/4611 ,  H05K3/4629 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/00012

摘要： A monolithic electronic component includes a composite body having a plurality of stacked ceramic layers. The ceramic layers include interconnecting conductors provided in each of the ceramic layers, including first terminals, arranged on a first end surface in the stacking direction of the composite body, for defining connections with an interconnection substrate, and second terminals, arranged on a second end surface opposite of the first end surface of the composite, for defining connections with a mounted component. The first terminals are defined by conductor layers provided on the first end surface and the second terminals are defined by exposed end surfaces of terminal via-hole conductors which extend from the inner portion of the composite to the second end surface. The exposed end surfaces of the terminal via-hole conductors are flat and are on substantially the same plane as the second end surface.

摘要翻译： 单片电子部件包括具有多个层叠陶瓷层的复合体。 陶瓷层包括设置在每个陶瓷层中的互连导体，包括第一端子，其布置在复合体的层叠方向上的第一端面上，用于限定与互连衬底的连接，以及布置在第二端上的第二端子 与复合材料的第一端面相对的表面，用于限定与安装部件的连接。 第一端子由设置在第一端面上的导体层限定，第二端子由从复合体的内部延伸到第二端面的端子通孔导体的暴露的端面限定。 端子通孔导体的露出端面是平坦的，并且与第二端面基本上在同一平面上。