公开(公告)号：US4653026A

公开(公告)日：1987-03-24

申请号：US403016

申请日：1982-07-29

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Satoru Ito ,  Toshimasa Kihara ,  Harumi Wakimoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Satoru Ito ,  Toshimasa Kihara ,  Harumi Wakimoto

IPC分类号： G11C11/40 ,  H01L27/088

CPC分类号： H01L27/088

摘要： A nonvolatile memory device comprising a plurality of memory cells composed of insulated gate-type field effect semiconductor elements, terminals for applying a writing voltage and a reading voltage to said plurality of memory cells, wirings for connecting in common insulated gate-type field effect transistor elements of said plurality of memory cells, and resistance elements or MISFET's which are connected between the wirings and the terminals, wherein said resistance elements or MISFET's are composed of a polycrystalline silicon film or a single crystal silicon film formed on the field insulation film.

摘要翻译： 一种非易失性存储器件，包括由绝缘栅型场效应半导体元件构成的多个存储单元，用于对所述多个存储单元施加写入电压和读取电压的端子，用于连接公共绝缘栅型场效应晶体管的布线 所述多个存储单元的元件，以及连接在布线和端子之间的电阻元件或MISFET，其中所述电阻元件或MISFET由形成在场隔离膜上的多晶硅膜或单晶硅膜构成。

公开(公告)号：US5159260A

公开(公告)日：1992-10-27

申请号：US4307

申请日：1987-01-07

申请人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

发明人： Kanji Yoh ,  Osamu Yamashiro ,  Satoshi Meguro ,  Koichi Nagasawa ,  Kotaro Nishimura ,  Harumi Wakimoto ,  Kazutaka Narita

IPC分类号： G05F3/24 ,  G11C5/14 ,  G11C11/411 ,  G11C11/417 ,  H01L27/088 ,  H01L29/49 ,  H03F3/45 ,  H03K3/0231 ,  H03K3/0233 ,  H03K3/3565 ,  H03K5/24 ,  H03K19/003 ,  H03K19/0185

CPC分类号： G11C11/4113 ,  G05F3/245 ,  G11C11/417 ,  G11C5/143 ,  G11C5/147 ,  H01L27/088 ,  H01L29/4983 ,  H03F3/45179 ,  H03F3/45744 ,  H03F3/45748 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018514 ,  H03K3/0231 ,  H03K3/02337 ,  H03K3/3565 ,  H03K5/2481 ,  H03F2203/45394

摘要： This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other. The channels of the first and second IGFETs have an identical conductivity type. On the basis of a self-alignment structure, at least those parts of first and second polycrystalline semiconductor regions being the gate electrodes of the first and second IGFETs which are proximate to source and drain regions are doped with the same impurity as that of the source and drain regions, and a central part of one of the first and second polycrystalline semiconductor regions is doped with an impurity of a selected one of the first conductivity type and the second conductivity type.

摘要翻译： 该参考电压发生器装置检测与半导体的能隙对应的电压或与其接近的值的电压或基于半导体的能级的电压，并产生检测电压作为参考电压。 通过检测第一和第二绝缘栅极场效应晶体管（IGFET）的阈值电压的差异来产生参考电压。 第一和第二IGFET的栅电极形成在基本相同条件下形成在相同半导体衬底的不同表面区域上的栅极绝缘膜上。 第一和第二IGFET的栅电极分别由选自第一导电类型的半导体，第二导​​电类型的半导体和由相同的半导体材料制成的本征半导体的两个半导体制成，并且具有费米 能量水平值彼此不同。 第一和第二IGFET的通道具有相同的导电类型。 基于自对准结构，至少第一和第二多晶半导体区域的那些部分是靠近源区和漏区的第一和第二IGFET的栅电极，其掺杂与源的相同杂质 和漏极区域，并且第一和第二多晶半导体区域之一的中心部分掺杂有选择的第一导电类型和第二导电类型的杂质。

公开(公告)号：US5189497A

公开(公告)日：1993-02-23

申请号：US765065

申请日：1991-09-24

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/06 ,  H01L27/105 ,  H01L29/788

CPC分类号： H01L29/7885 ,  H01L27/105 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US20060014347A1

公开(公告)日：2006-01-19

申请号：US11220723

申请日：2005-09-08

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/336

CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

公开(公告)号：US5629541A

公开(公告)日：1997-05-13

申请号：US422940

申请日：1995-04-17

申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886 ,  G11C16/0416 ,  H01L27/0688

摘要： A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.

摘要翻译： 在具有场效应晶体管的非易失性存储器电路中具有非易失性存储元件或单元型存储单元的半导体集成器件，除了用于存储信息的浮栅电极和控制栅极之外， 电极，其包括具有从其主表面延伸的半导体衬底的深度的重掺杂区域。 此外，单元件型场效应晶体管具有漏极，其包括从其主表面延伸到半导体衬底中的深度较小的轻掺杂区域。

公开(公告)号：US5445980A

公开(公告)日：1995-08-29

申请号：US147037

申请日：1993-11-04

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Hitoshi Kume ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Hitoshi Kume ,  Hideaki Yamamoto

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/423

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

摘要： An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.

摘要翻译： EEPROM（电可擦除可编程只读存储器）具有其源极区域附近的每个存储单元MISFET的浮置栅极的角部为圆形的结构。 通过以下方法制造EEPROM：其特征在于，高浓度杂质的离子与存储单元MISFET的浮置栅极电极和控制栅极电极自对准，以形成其源极和漏极区域， 于是进行氧化处理。

公开(公告)号：US5340760A

公开(公告)日：1994-08-23

申请号：US992473

申请日：1992-12-15

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： A01H5/02 ,  H01L27/06 ,  H01L27/105 ,  H01L29/788 ,  H01L21/335

CPC分类号： A01H5/02 ,  H01L27/105 ,  H01L29/7885 ,  H01L29/7886 ,  H01L27/0688

摘要： This invention discloses EEPROM which increases an erasing voltage V.sub.pp to be applied in a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in order to improve erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carrier be easily generated and to improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期中施加的擦除电压Vpp，以提高擦除效率，并采用这样的结构， 边缘，以便容易地产生热载体并提高写入效率。

公开(公告)号：US5153144A

公开(公告)日：1992-10-06

申请号：US794648

申请日：1991-11-18

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Hitoshi Kume ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Hitoshi Kume ,  Hideaki Yamamoto

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/423

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/11546 ,  H01L29/42324

摘要： An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.

摘要翻译： EEPROM（电可擦除可编程只读存储器）具有其源极区域附近的每个存储单元MISFET的浮置栅极的角部为圆形的结构。 通过以下方法制造EEPROM：其特征在于，将高剂量杂质的离子与存储单元MISFET的浮置栅电极和控制栅电极自对准地注入，以形成其源区和漏区， 于是进行氧化处理。

公开(公告)号：US5079603A

公开(公告)日：1992-01-07

申请号：US517386

申请日：1990-04-30

申请人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

发明人： Kazuhiro Komori ,  Satoshi Meguro ,  Takaaki Hagiwara ,  Hitoshi Kume ,  Toshihisa Tsukada ,  Hideaki Yamamoto

IPC分类号： H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7886 ,  H01L27/105 ,  H01L27/0688

摘要： This invention discloses an EEPROM which increases an erasing voltage V.sub.pp to be applied during a data write cycle by increasing an avalanche breakdown voltage between a source region and a semiconductor substrate in the memory cell transistor in order to improve the erasing efficiency, and employs a structure which strengthens the electric field at the edge of a drain region in order to let hot carriers be easily generated and to thereby improve writing efficiency.

摘要翻译： 本发明公开了一种EEPROM，其通过增加存储单元晶体管中的源极区域和半导体衬底之间的雪崩击穿电压来增加在数据写入周期期间施加的擦除电压Vpp，以提高擦除效率，并采用结构 这加强了漏极区域的边缘处的电场，以便容易地产生热载流子，从而提高写入效率。