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1.发明授权
公开(公告)号：US5949097A
公开(公告)日：1999-09-07
申请号：US932939
申请日：1997-09-17
IPC分类号： H01L21/331 , H01L21/768 , H01L27/06 , H01L29/737 , H01L29/04
CPC分类号： H01L29/66318 , H01L27/0605 , H01L29/7371
摘要： The present invention relates to a contact structure not only for a semiconductor device having a hetero-junction bipolar transistor or a hetero-insulated gate field effect transistor but also for semiconductor devices at large. In a semiconductor layer of a polycrystalline or amorphous undoped III-V compound semiconductor or an alloy thereof, a through hole is formed for contact. The size of the through hole is set to permit exposure of at least part of a first conductor layer and a dielectric layer, such as an Si compound, present around the first conductor layer, and a second conductor layer is formed within the through hole so as to contact the first conductor layer. Since the semiconductor layer can be subjected to a selective dry etching for the dielectric layer, the dielectric layer is not etched at the time of forming the above through hole in the semiconductor layer. As a result an electric short-circuit of the second conductor layer with a single crystal semiconductor layer which underlies the dielectric layer can be prevented.
摘要翻译： 本发明涉及不仅具有异质结双极晶体管或异质绝缘栅场效应晶体管的半导体器件的接触结构，而且还涉及用于半导体器件的半导体器件。 在多晶或非晶未掺杂的III-V族化合物半导体的半导体层或其合金中，形成用于接触的通孔。 通孔的尺寸被设定为允许暴露在第一导体层周围的第一导体层和诸如Si化合物的电介质层的至少一部分，并且在通孔内形成第二导体层，因此 以接触第一导体层。 由于可以对半导体层进行电介质层的选择性干蚀刻，所以在形成半导体层中的上述通孔时不会蚀刻电介质层。 结果，可以防止具有位于电介质层下面的单晶半导体层的第二导体层的电短路。
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2.发明授权
公开(公告)号：US5017517A
公开(公告)日：1991-05-21
申请号：US518035
申请日：1990-05-02
IPC分类号： H01L29/73 , H01L21/20 , H01L21/28 , H01L21/331 , H01L29/205 , H01L29/737 , H01L29/80
CPC分类号： H01L29/66318 , H01L21/02395 , H01L21/02463 , H01L21/02491 , H01L21/02546 , H01L21/02639 , H01L21/28 , Y10S148/005 , Y10S148/011 , Y10S148/026 , Y10S438/976
摘要： A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.
摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一半导体层，形成锑（Sb）的表面保护层或具有Sb的材料作为其主要成分，执行制造所需的其它步骤 半导体器件，去除表面保护层，并且在由此暴露的第一半导体层上形成第二半导体层。
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公开(公告)号：US5481120A
公开(公告)日：1996-01-02
申请号：US164801
申请日：1993-12-10
申请人： Kazuhiro Mochizuki , Tomoyoshi Mishima , Tohru Nakamura , Hiroshi Masuda , Tomonori Tanoue , Tooru Haga , Yoshihisa Fujisaki
发明人： Kazuhiro Mochizuki , Tomoyoshi Mishima , Tohru Nakamura , Hiroshi Masuda , Tomonori Tanoue , Tooru Haga , Yoshihisa Fujisaki
IPC分类号： H01L21/331 , H01L29/08 , H01L29/20 , H01L29/45 , H01L29/737 , H01L29/80 , H01S5/042 , H01S5/183 , H01S5/22 , H01S5/323 , H01L27/02
CPC分类号： H01S5/18347 , H01L29/0891 , H01L29/20 , H01L29/452 , H01L29/66318 , H01L29/7371 , H01S5/0424 , H01L29/802 , H01S2304/02 , H01S5/18341 , H01S5/18369 , H01S5/32316
摘要： Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more. In the case that the above polycrystaline compound semiconductor layer with a low resistance is used as an extrinsic base region of an heterojunction bipolar transistor, since the extrinsic base region can be formed on a dielectric film formed on a collector, it is possible to reduce the base-collector capacitance, and hence to enhance the operational speed of the heterojunction bipolar transistor.
摘要翻译： 公开了使用具有低电阻的多晶化合物半导体作为低电阻层的半导体器件及其制造方法。 上述多晶化合物半导体层以C或Be作为杂质被大量掺杂，并且电阻极低。 多晶化合物半导体层通过分子束外延法，有机金属气相外延法和有机金属分子束外延法中的任一种形成，在基板温度为450℃以下的条件下， 对于III族元素的V族元素为50以上。 在上述具有低电阻的多晶化合物半导体层用作异质结双极晶体管的外在基极区域的情况下，由于可以在形成在集电体上的电介质膜上形成非本征基区，因此可以减少 基极集电极电容，从而提高异质结双极晶体管的工作速度。
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4.发明授权
公开(公告)号：US5598015A
公开(公告)日：1997-01-28
申请号：US357342
申请日：1994-12-15
IPC分类号： H01L29/205 , H01L21/331 , H01L29/73 , H01L29/737 , H01L31/0328 , H01L27/082 , H01L31/0336
CPC分类号： H01L29/66318 , H01L29/7371
摘要： A hetero-junction bipolar transistor having an emitter composed of a semiconductor having a wider forbidden band width than that of a semiconductor constituting a base is disclosed. In the transistor, the emitter and the electrode leader area composed of a single crystalline semiconductor are provided being extended from the upper part of the emitter to the surface of the base through an insulating layer, for the purpose of making it possible to miniaturize the transistor and to operate the transistor at a high-speed by decreasing the emitter resistance.
摘要翻译： 公开了一种异质结双极晶体管，其具有由具有比构成基极的半导体宽的禁带宽度的半导体构成的发射极。 在晶体管中，由单晶半导体构成的发射极和电极引出区域通过绝缘层从发射极的上部延伸到基底的表面，以便使晶体管小型化 并通过降低发射极电阻来高速运行晶体管。
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5.发明授权Hetero junction bipolar transistor with improved electrode wiring contact region 失效具有改进的电极接线区域的异质结双极晶体管
公开(公告)号：US5296733A
公开(公告)日：1994-03-22
申请号：US615381
申请日：1990-11-19
申请人： Chushiroh Kusano , Hiroshi Masuda , Katsuhiko Mitani , Kazuhiro Mochizuki , Masaru Miyazaki , Masahiko Kawata , Susumu Takahashi
发明人： Chushiroh Kusano , Hiroshi Masuda , Katsuhiko Mitani , Kazuhiro Mochizuki , Masaru Miyazaki , Masahiko Kawata , Susumu Takahashi
IPC分类号： H01L29/73 , H01L21/331 , H01L29/205 , H01L29/737 , H01L29/72 , H01L29/06
CPC分类号： H01L29/7371
摘要： A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.
摘要翻译： 异质结双极晶体管提供接触区域，其在发射极（或集电极）电极和形成在电极上的布线之间的面积大于发射极（或集电极）的面积。 防止施加到发射极（或集电极） - 基极结的电压变化，并且获得晶体管的稳定操作。 另外，当进行蚀刻操作时，在掩模的侧面上形成绝缘膜。 然后执行发射极（或集电极）的图案化，因此形成具有接近于掩模的尺寸的发射极（或集电极）。
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公开(公告)号：US5668402A
公开(公告)日：1997-09-16
申请号：US66635
申请日：1993-05-24
申请人： Kazuhiro Mochizuki , Shigeo Goto , Chushirou Kusano , Masahiko Kawata , Hiroshi Masuda , Katsuhiko Mitani , Susumu Takahashi
发明人： Kazuhiro Mochizuki , Shigeo Goto , Chushirou Kusano , Masahiko Kawata , Hiroshi Masuda , Katsuhiko Mitani , Susumu Takahashi
IPC分类号： H01L29/73 , A61F7/02 , H01L21/20 , H01L21/331 , H01L21/338 , H01L29/04 , H01L29/205 , H01L29/737 , H01L29/812
CPC分类号： H01L29/045 , H01L21/02395 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02532 , H01L21/02546 , H01L21/02609 , A61F2007/0265
摘要： A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.
摘要翻译： 半导体器件包括由第一单晶半导体材料形成的半导体衬底和通过掺杂有易于表面分离的元件的第二单晶半导体材料形成在半导体衬底上的半导体层。 半导体衬底的表面由与第二单晶半导体材料的表面上形成的小平面基本相同的晶面形成，如果第二单晶半导体材料被外延生长，在第 100）平面的第一单晶半导体材料。
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公开(公告)号：US09089306B2
公开(公告)日：2015-07-28
申请号：US12734045
申请日：2008-09-16
申请人： Chikao Harada , Hiroshi Masuda , Hidenori Suzuki
发明人： Chikao Harada , Hiroshi Masuda , Hidenori Suzuki
CPC分类号： A61B5/489 , A61B5/6835 , A61B8/0891 , A61B8/4218 , A61B8/4281 , A61B8/4483 , A61B8/4494 , A61B8/464 , A61B8/488 , G01S7/52065 , G01S15/8925 , G01S15/8936
摘要： A blood vessel ultrasonic image measuring method capable of facilitating the positioning of an ultrasonic probe and acquiring sufficient positioning accuracy. Because of inclusion of an around-X-axis positioning step of causing a multiaxis driving device to position an ultrasonic probe such that distances from respective ultrasonic array probes to the center of a blood vessel are equalized, and an X-axis direction positioning step and an around-Z-axis positioning step of causing the multiaxis driving device to position the ultrasonic probe such that the image of the blood vessel is positioned at the center portion in the width direction of the first short axis image display area and the second short axis image display area, the positioning may be performed by using the positions in the longitudinal direction of the ultrasonic array probes relative to the blood vessel or the distances of the ultrasonic array probes to the blood vessel.
摘要翻译： 一种血管超声波图像测量方法，其能够促进超声波探头的定位并获得足够的定位精度。 由于包含使X轴方向定位工序和多轴驱动装置定位超声波探头的X轴定位步骤，使得从各个超声波阵列探针到血管中心的距离相等， 绕Z轴定位步骤，使多轴驱动装置定位超声波探头，使得血管的图像位于第一短轴图像显示区域和第二短轴图像显示区域的宽度方向上的中心部分 可以通过使用超声波阵列探针相对于血管的纵向方向的位置或超声阵列探针到血管的距离来进行定位。
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公开(公告)号：US08928225B2
公开(公告)日：2015-01-06
申请号：US13379708
申请日：2010-07-23
CPC分类号： G09G3/14 , B60K35/00 , B60K2350/203 , G01D7/00 , G09F9/33 , G09G2320/0247 , G09G2380/10
摘要： Provided is a display device in which design properties have been improved by eliminating the flickering when the display level changes. A microcomputer (5) causes light emission of first LEDs (23 and 24) which are the first and second ones counting from the right end among the emitting first LEDs (21 to 24), with decreasing brightness towards the right end. Furthermore, the microcomputer (5) causes light emission of second LEDs from a second LED (77) which is disposed at the right end of the second LEDs (71 to 77), to a second LED (73) which is disposed at a position overlapped with the first LEDs (23 and 24) that emit light with decreasing brightness towards the right end, and also causes light emission of second LEDs (73 and 74), which are the first and second ones counting from the left end among the emitting second LEDs (73 to 77), with decreasing brightness towards the left end.
摘要翻译： 提供了一种显示装置，其中通过在显示电平变化时消除闪烁来改善设计特性。 微型计算机（5）使作为第一和第二LED的第一LED（23和24）的光从第一发光二极管（21〜24）的右端开始发光，朝向右端的亮度降低。 此外，微型计算机（5）将第二LED（77）的第二LED（77）发光到设置在第二LED（71〜77）的右端的第二LED（77）的第二LED（73） 与朝向右端发光的亮度发光的第一LED（23和24）重叠，并且还引起第二LED（73和74）的发光，第二LED（73和74）是从发射的左端计数的第一和第二LED 第二个LED（73至77），朝向左端的亮度降低。
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公开(公告)号：US08754723B2
公开(公告)日：2014-06-17
申请号：US13211355
申请日：2011-08-17
申请人： Hiroshi Masuda , Takahiro Mori
发明人： Hiroshi Masuda , Takahiro Mori
CPC分类号： H01P5/187
摘要： External electrodes are provided on a bottom surface of a laminate, and are connected to both ends of a main line and both ends of a sub-line, respectively. A warpage prevention conductor is provided on an insulating material layer that is provided on a top surface side of the laminate with respect to insulating material layers to which the main line is provided and with respect to insulating material layers to which the sub-line is provided. The warpage prevention conductor overlaps with the external electrodes when seen from a z-axis direction in a plan view. A conductor layer that is not connected to the main line or the sub-line is not provided on any of the insulating material layers provided on a bottom surface side of the laminate with respect to the insulating material layer on which the warpage prevention conductor is provided.
摘要翻译： 外部电极设置在层叠体的底面上，分别连接在主线和副线的两端的两端。 防翘曲导体设置在绝缘材料层上，该绝缘材料层设置在相对于设置有主线的绝缘材料层的层叠体的顶表面侧，并且相对于设置有子线的绝缘材料层 。 在俯视图中，从z轴方向观察时，翘曲防止导体与外部电极重叠。 没有连接到主线或子线的导体层不设置在相对于其上提供防翘曲导体的绝缘材料层设置在层叠体的底表面侧上的任何绝缘材料层上 。
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10.发明申请公开(公告)号：US20110235964A1
公开(公告)日：2011-09-29
申请号：US13061314
申请日：2009-08-28
CPC分类号： G02B6/4214 , G02B6/138 , H01L2224/48091 , H01L2224/48137 , H05K1/0274 , H05K1/183 , H05K3/365 , H01L2924/00014
摘要： The present invention relates to an optical waveguide comprising a lower cladding layer, a patternized core layer and an upper cladding layer, wherein a striking part for positioning is provided in one end part thereof, and an optical path turning mirror face is formed in a position different from a striking part-forming end part in the above core layer.Capable of being provided are an optical waveguide and an optoelectronic circuit board each having a simple configuration in which an optical device is not mounted on an optical wiring part or an optoelectronic composite wiring part and capable of connecting an optical device with a core of an optical waveguide in an optical wiring part (optical waveguide) or an optoelectronic composite wiring part (optoelectronic circuit board) at a high position accuracy and an optical module comprising an optical waveguide or an optoelectronic circuit board and a connector.
摘要翻译： 本发明涉及一种包括下包层，图案化核心层和上包层的光波导，其中在其一个端部设置有用于定位的击打部分，并且光路转向镜面形成在一个位置 与上述芯层中的打击部分形成端部不同。 能够提供的是光波导和光电子电路板，其具有简单的配置，其中光学装置不安装在光布线部分或光电复合布线部分上，并且能够将光学装置与光学芯部连接 光学配线部（光波导路）或光电子复合配线部（光电子电路基板）的高精度的波导管以及包括光波导或光电子电路基板以及连接器的光学模块。
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