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    Integrated circuit carrier having lead-socket array with various inner dimensions
    1.
    发明授权
    Integrated circuit carrier having lead-socket array with various inner dimensions 失效
    集成电路载体，具有各种内部尺寸的导线插座阵列

    公开(公告)号：US5763297A

    公开(公告)日：1998-06-09

    申请号：US597113

    申请日：1996-02-06

    申请人： Kazuhiro Tashiro ,  Tetsushi Wakabayashi

    发明人： Kazuhiro Tashiro ,  Tetsushi Wakabayashi

    IPC分类号： H01L23/00 ,  G01R1/04 ,  H05K3/30 ,  H05K7/10 ,  H01L21/60

    CPC分类号： G01R1/0433 ,  H05K7/1084 ,  H05K3/306

    摘要： An IC carrier on which an integrated circuit (IC) package is loaded when electric testing of the IC package is carried out is described. The present invention enables an IC package to be loaded on or unloaded from the IC carrier smoothly without bending any of closely arranged fine leads, and prevents the lead from being deformed by falling impact when it is dropped. According to the present invention, an IC carrier for an IC package having an array of leads comprises an array of socket means for mating with the array of leads, wherein selected one of said socket means differs in an inner dimension from the other ones in the same array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

    摘要翻译： 描述了在IC封装的电测试执行时装载集成电路（IC）封装的IC载体。 本发明使得IC封装能够平稳地装载或卸载IC载体，而不会弯曲任何紧密排列的细导线，并且防止引线在跌落时由于冲击而变形。 根据本发明，用于具有引线阵列的IC封装的集成电路载体包括用于与导线阵列配合的插座装置阵列，其中所述插座装置中选定的一个在内部尺寸上与 相同的数组。 该技术适用于扁平IC封装（QFP或SOP）和引脚格栅阵列IC封装（PGA）。

    Integrated circuit carrier having lead-socket array with various inner dimensions
    2.
    发明授权
    Integrated circuit carrier having lead-socket array with various inner dimensions 失效
    集成电路载体，具有各种内部尺寸的导线插座阵列

    公开(公告)号：US5668407A

    公开(公告)日：1997-09-16

    申请号：US673095

    申请日：1996-07-01

    申请人： Kazuhiro Tashiro ,  Tetsushi Wakabayashi

    发明人： Kazuhiro Tashiro ,  Tetsushi Wakabayashi

    IPC分类号： H01L23/00 ,  G01R1/04 ,  H05K3/30 ,  H05K7/10 ,  H01L23/48

    CPC分类号： G01R1/0433 ,  H05K7/1084 ,  H05K3/306

    摘要： An IC carrier for electric testing of an IC package enables an IC package to be loaded on or unloaded from it smoothly without bending any of closely arranged fine leads, and prevents the leads from being deformed by falling impact when it is dropped. The IC carrier for an IC package, having an array of leads, comprises an array of sockets for mating with the array of leads, wherein selected one of the sockets differs in clearance between a width of each of the sockets and a width of each of the leads to be mated from the other ones in a cross section of an array. For instance, an array of sockets having holes to mate with leads having a single diameter of an IC package are arranged so that inner diameters of the holes in an outer part of the array is larger than those in a central part of the array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

    摘要翻译： 用于IC封装的电测试的IC载体使得IC封装能够平滑地装载或卸载IC封装，而不会弯曲任何紧密排列的细小引线，并且防止引线在跌落时由于冲击而变形。 用于具有引线阵列的IC封装的IC载体包括用于与引线阵列配合的插座阵列，其中插座中的选定一个插座间隙在每个插座的宽度和每个插座的宽度之间的间隙 导线与阵列的横截面中的其他导线相交。 例如，具有与IC封装的单一直径的引线相配合的孔的插座阵列被布置成使得阵列的外部部分中的孔的内径大于阵列的中心部分中的孔的内径。 该技术适用于扁平IC封装（QFP或SOP）和引脚格栅阵列IC封装（PGA）。

    Tray in combination with electronic component attaching tool attached to the tray
    3.
    发明授权
    Tray in combination with electronic component attaching tool attached to the tray 失效
    托盘与附在托盘上的电子元件连接工具组合

    公开(公告)号：US08671557B2

    公开(公告)日：2014-03-18

    申请号：US13242647

    申请日：2011-09-23

    申请人： Daisuke Koizumi ,  Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Naoyuki Watanabe

    发明人： Daisuke Koizumi ,  Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Naoyuki Watanabe

    IPC分类号： B23P19/00

    CPC分类号： B25B27/14 ,  H05K7/1061 ,  Y10T29/4913 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53187 ,  Y10T29/53191 ,  Y10T29/53943

    摘要： A tray is provided in combination with an electronic component attaching tool attached to the tray and includes an attachment depression part that includes an inner wall and to which an electronic component is attached, wherein forming of the inner wall of the attachment depression part does not substantially depend on an external shape of the electronic component, and a standard part formed in the inner wall of the attachment depression part and engaging with a first structure part of the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to a first position of the tray using the electronic component attaching tool, the standard part having a shape which does not substantially depend on the external shape of the electronic component.

    摘要翻译： 托盘与附接到托盘上的电子部件连接工具组合地提供，并且包括附接凹陷部分，该附件凹陷部分包括内壁并且附接有电子部件，其中，附接凹陷部分的内壁的形成基本上不 取决于电子部件的外部形状，以及形成在安装凹部的内壁中的标准部分，并与电子部件安装工具的第一结构部分接合，以将电子部件安装工具的位置对准到标准 当使用电子部件安装工具将电子部件的位置与托盘的第一位置对准时，标准部件具有基本上不依赖于电子部件的外形的形状。

    Semiconductor device packaging structure
    4.
    发明授权
    Semiconductor device packaging structure 有权
    半导体器件封装结构

    公开(公告)号：US08164181B2

    公开(公告)日：2012-04-24

    申请号：US12872131

    申请日：2010-08-31

    申请人： Kazuhiro Tashiro ,  Keisuke Fukuda ,  Naohito Kohashi ,  Shigeyuki Maruyama

    发明人： Kazuhiro Tashiro ,  Keisuke Fukuda ,  Naohito Kohashi ,  Shigeyuki Maruyama

    IPC分类号： H01L23/12

    CPC分类号： H01L21/67333 ,  H01L21/50 ,  H01L22/20 ,  H01L23/04 ,  H01L23/544 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/1616 ,  H01L2924/166 ,  Y10T29/49826 ,  H01L2924/00

    摘要： A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.

    摘要翻译： 公开了一种半导体器件封装结构，其可以提高半导体器件的性能测试的可靠性，并防止在运输或包装期间对半导体器件的损坏。 由于包含半导体芯片和具有不同高度的电气部件，所以具有高度不均匀性的半导体器件附着IC盖。 IC盖包括突出部分和基部。 在安装到半导体器件之后，突出部分位于半导体器件中的自由区域中，并且基底部分由与半导体芯片和半导体器件中的电气部件分离的突起支撑。 IC盖可拆卸地附接到半导体器件。

    PROBER, TESTING APPARATUS, AND METHOD OF INSPECTING SEMICONDUCTOR CHIP
    5.
    发明申请
    PROBER, TESTING APPARATUS, AND METHOD OF INSPECTING SEMICONDUCTOR CHIP 有权
    探测器，测试装置和检查半导体芯片的方法

    公开(公告)号：US20110254574A1

    公开(公告)日：2011-10-20

    申请号：US13168719

    申请日：2011-06-24

    申请人： Kazuhiro Tashiro

    发明人： Kazuhiro Tashiro

    IPC分类号： G01R31/308 ,  G01R31/00 ,  G01N21/00 ,  G01R31/26

    CPC分类号： G01R31/2887 ,  G01R31/2891

    摘要： A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.

    摘要翻译： 探针包括设置有支撑板的探针卡和附接到支撑板的探针，安装有测量晶片的台，设置在探针卡上方的照相机，以观察形成在第一半导体芯片上的第一半导体芯片的电极焊盘 测量晶片和用于相对于探针卡移动台的位置的台移动单元。

    Semiconductor testing device
    7.
    发明授权
    Semiconductor testing device 有权
    半导体测试装置

    公开(公告)号：US07161370B2

    公开(公告)日：2007-01-09

    申请号：US11046883

    申请日：2005-02-01

    申请人： Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Makoto Haseyama

    发明人： Shigeyuki Maruyama ,  Kazuhiro Tashiro ,  Makoto Haseyama

    IPC分类号： G01R31/26

    CPC分类号： G01R31/308 ,  G01R31/302 ,  H01L2924/0002 ,  H05K3/326 ,  H01L2924/00

    摘要： A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed therein at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.

    摘要翻译： 半导体测试装置用于测试具有至少一个球形连接端子的半导体器件。 该测试装置包括：绝缘基板，其在与球形连接端子的位置对应的位置处形成有开口;以及接触部件，形成在绝缘基板上，包括与球形连接端子连接的连接部， 所述连接部分至少可变形并延伸到所述开口中。

    Composition for hair treatment
    10.
    发明授权
    Composition for hair treatment 失效
    头发处理组成

    公开(公告)号：US5374421A

    公开(公告)日：1994-12-20

    申请号：US978192

    申请日：1992-11-18

    申请人： Kazuhiro Tashiro ,  Kazuyuki Yahagi

    发明人： Kazuhiro Tashiro ,  Kazuyuki Yahagi

    IPC分类号： A61K8/00 ,  A61K8/34 ,  A61K8/41 ,  A61K8/89 ,  A61K8/891 ,  A61K8/893 ,  A61K8/92 ,  A61Q5/00 ,  A61Q5/02 ,  A61Q5/12 ,  C08L83/04 ,  A61K7/09

    CPC分类号： A61K8/345 ,  A61K8/342 ,  A61K8/416 ,  A61K8/893 ,  A61Q5/02 ,  A61Q5/12

    摘要： A composition for hair treatment such as hair rinse, shampoo, or hair conditioner, contains (a) 0.1-10 wt. % of a modified silicone polymer having at least one alkoxy group in the molecule and a melting point of not lower than 30.degree. C., (b) 0.1-20 wt. % of a cationic surface active agent, (c) 0.1-30 wt. % of an oily or fatty material, (d) 0.1-90 wt. % of an organic liquid which is compatible with water and of which molecule has at least one hydroxy group, and (e) water.

    摘要翻译： 用于毛发处理的组合物如洗发剂，洗发剂或护发素包含（a）0.1-10重量％ ％的分子中具有至少一个烷氧基并且熔点不低于30℃的改性硅氧烷聚合物，（b）0.1-20重量％ ％的阳离子表面活性剂，（c）0.1-30重量％ ％的油性或脂肪材料，（d）0.1-90重量％ ％的与水相容的分子和至少一个羟基的有机液体，和（e）水。