摘要:
A digital signal processor for determining the maximum and minimum values of a plurality of data items wherein operations of an arithmetic logic unit and data memories are controlled by micro-instructions, including a device for decoding specified bits of an operand of the micro-instruction, a device for detecting a value of a condition code which has been designated by an output of the decoding device, and a control device for executing a logical operation between the output of the detection device, which becomes "1" if the value of the condition code is true, and a decoded value of an operation code of the micro-instruction and to generate a control signal for the arithmetic logic unit on the basis of a result of the logical operation.
摘要:
A processor comprises first and second operation units, a first program memory which contains first microinstructions for controlling the first operation unit and second microinstructions for controlling at least the second operation units, a second program memory which contains microinstructions for controlling the second operation unit, first control means connected to the first program memory for controlling the first operation unit and the second operation unit, and second control means connected to the second program memory for controlling the second operation unit. In a normal mode, all operation units are under control of the first control means and in a multiprogram mode, the first operation unit is under control of the first control means and the second operation unit is under control of the second control means. These two mode operations are selected in accordance with the microinstructions stored in the first or second program memories.
摘要:
A high-speed multiplier adapted to VLSI with a regularly arranged structure having a reduced number of addition stages. There is provided a carry save adder circuit wherein a time difference is imparted to signals input to full adders, in order to eliminate extra wait time in the signal propagation. That is, a carry signal of a full adder of two stages over is input with a speed increase of 1/2T.sub.FA.
摘要:
A memory circuit is divided into a plurality of memory blocks, and an address register and a delay register are disposed in each memory block. Therefore, a read or write operation and a shifting operation of the address for storing data inside a memory matrix can be realized by a pipeline technique, and hence a memory circuit having a high processing speed is obtained.
摘要:
An LSI system is disclosed in which a plurality of status registers for indicating the internal status of the system are connected to each other so as to form a hierarchical structure and the contents of each of the remaining status registers other than one status register can be transferred to an output register through a bus, to make it possible to provide additional status registers in the system without increasing the number of address signals used and the number of pins connected to external address signal lines.
摘要:
A multi-processor system for multidimensional image signal processing includes a plurality of co-processors and a host processor which issues processor numbers and a command to the co-processors through a bus. Due to the multi-dimensional nature of the processor numbers, data processing for given ranges of an image signal can be shared by the co-processors. A particular multi-dimensional processor number issued by the host computer which allows simultaneous communication to be performed between the host processor and the co-processors.
摘要:
This invention relates to an information processing apparatus such as a digital signal processor and is applied particularly suitably to a digital filter.A plurality of data from initial value data till final value data relating to filtering coefficients of a digital filter are stored in a data memory, and are sequentially read out by an increment operation of an address arithmetic unit.A data arithmetic unit executes sequentially product and/or sum operations of a plurality of data that are sequentially read out and digital input signals that are sequentially inputted, to perform digital signal processing.The information processing apparatus is equipped particularly with means, which when an access address starts from an initial value, exceeds a final value and reaches a return address due to the increment operation, returns automatically the access address to the initial value. Therefore, a plurality of data stored in the data memory can be utilized repeatedly.Contrivances are made in order to set the number of a plurality of data that are stored in the data memory for repetition of use, to an arbitrary value.
摘要:
A semiconductor integrated circuit device formed on a single chip or a microcomputer integrated on a semiconductor chip includes a central processing unit (CPU), an interface circuit (or an input/output port), a bus coupled to the CPU and the interface circuit (or the input/output port) and a variable logic circuit (or a subprocessor). The variable logic circuit (or the subprocessor) includes non-volatile memory elements storing instructions, a control circuit generating control signals in accordance with the stored instructions, and an arithmetic logic unit controlled by the generated control signals. Information can be written into the non-volatile memory elements from outside to construct the variable logic circuit or the subprocessor with any desired logical functions. The wiring operation of the memory elements can be executed in a short time, and a user can thus quickly obtain a single-chip microprocessor or a single-chip semiconductor integrated circuit device having hardware of peculiar prescribed specifications.
摘要:
A typical single chip microcomputer disclosed in the present application comprises a control circuit, a processing circuit and a plurality of address register--status register pairs. A logical unit formed within the control circuit comprises an electrically writable non-volatile-semiconductor memory device. Information can be externally written into the non-volatile semiconductor memory included in the logical unit, and the above described plurality of address register--status register pairs can be arbitrarily selected. As a result, logic function of the logical unit can be arbitrarily established in accordance with externally supplied information. Demanded specifications of various users can be satisfied by the logic function thus arbitrarily formed.
摘要:
A method of diagnosis of an integrated logic circuit having function blocks, in which a test signal is supplied to the logic circuit; an input signal to and an output signal from at least one of the function blocks are detected by the use of a contactless probing device such as an electron beam probing device or laser beam probing device; simulation is carried out of a normal logic operation of the function block with the detected input signal to provide a simulated output signal; the detected and simulated output signals are compared with each other; and the function block is determined as being normal or abnormal according to the result of the comparison. When the function block includes plural logic elements, the cause of the abnormality may be traced back to a faulty function element by detecting the output of a function element by a contactless probing device, comparing the detected output with a corresponding simulated output and repeating the detection and comparison on other function elements in the function block until the comparison results in coincidence. The function element which receives the signal providing the coincidence as a result of the comparison is determined as the faulty function element.