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    Nonvolatile memory utilizing hot-carrier effect with data reversal function
    1.
    发明申请
    Nonvolatile memory utilizing hot-carrier effect with data reversal function 有权
    使用具有数据反转功能的热载波效应的非易失性存储器

    公开(公告)号：US20080186767A1

    公开(公告)日：2008-08-07

    申请号：US11701958

    申请日：2007-02-02

    申请人： Takashi Kikuchi ,  Kenji Noda

    发明人： Takashi Kikuchi ,  Kenji Noda

    IPC分类号： G11C16/06

    CPC分类号： G11C14/00 ,  G11C14/0063

    摘要： A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.

    摘要翻译： 非易失性半导体存储器件包括控制电路，反相电路和存储器单元，每个存储器单元包括具有第一节点和第二节点的锁存器，板线，具有源/漏节点之一的第一MIS晶体管 耦合到锁存器的第一节点，耦合到板线的源极/漏极节点中的另一个以及耦合到字线的栅极节点以及耦合到第二节点的源极/漏极节点之一的第二MIS晶体管 耦合到板线的源/漏节点中的另一个和耦合到字线的栅极节点，其中控制电路被配置为通过从锁存器读取数据来反转锁存在锁存器中的数据， 使反相电路反转读取的数据，并将反相数据写入锁存器。

    Nonvolatile memory utilizing MIS memory transistors with function to correct data reversal
    2.
    发明授权
    Nonvolatile memory utilizing MIS memory transistors with function to correct data reversal 有权
    使用MIS存储晶体管的非易失性存储器具有校正数据反转的功能

    公开(公告)号：US07639546B2

    公开(公告)日：2009-12-29

    申请号：US12037414

    申请日：2008-02-26

    申请人： Takashi Kikuchi ,  Kenji Noda

    发明人： Takashi Kikuchi ,  Kenji Noda

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1045 ,  G11C7/1006 ,  G11C7/12 ,  G11C14/00 ,  G11C14/0063

    摘要： A nonvolatile semiconductor memory device includes a latch circuit having two nodes, a nonvolatile memory cell including two MIS transistors, a bit swapping unit configured to provide straight connections between the two nodes and the two MIS transistors during a first operation mode and to provide cross connections between the two nodes and the two MIS transistors during a second operation mode, and a control circuit configured to cause, in one of the first and second operation modes, the nonvolatile memory cell to store the data latched in the latch circuit as an irreversible change of transistor characteristics occurring in a selected one of the two MIS transistors, and further configured to cause, in another one of the first and second operation modes, the latch circuit to detect the data stored in the nonvolatile memory cell.

    摘要翻译： 非易失性半导体存储器件包括具有两个节点的锁存电路，包括两个MIS晶体管的非易失性存储器单元，配置成在第一操作模式期间在两个节点和两个MIS晶体管之间提供直连接并提供交叉连接 在第二操作模式期间在两个节点和两个MIS晶体管之间，以及控制电路，被配置为在第一和第二操作模式之一中使得非易失性存储单元将锁存在锁存电路中的数据存储为不可逆变化 的晶体管特性出现在所述两个MIS晶体管中的所选择的一个中，并且还被配置为在所述第一和第二操作模式中的另一个中引起所述锁存电路来检测存储在所述非易失性存储单元中的数据。

    Nonvolatile memory utilizing MIS memory transistors capable of multiple store operations
    3.
    发明授权
    Nonvolatile memory utilizing MIS memory transistors capable of multiple store operations 有权
    使用能够进行多个存储操作的MIS存储器晶体管的非易失性存储器

    公开(公告)号：US07518917B2

    公开(公告)日：2009-04-14

    申请号：US11775951

    申请日：2007-07-11

    申请人： Kenji Noda ,  Takashi Kikuchi

    发明人： Kenji Noda ,  Takashi Kikuchi

    IPC分类号： G11C11/34

    CPC分类号： G11C14/00 ,  G11C11/412

    摘要： A nonvolatile semiconductor memory device includes a latch configured to store data, a plurality of word lines, a driver configured to activate one of the plurality of word lines, and a plurality of nonvolatile memory cells coupled to the respective word lines, each of the nonvolatile memory cells coupled to the latch so as to exchange stored data with the latch upon activation of a corresponding one of the word lines, each of the nonvolatile memory cells including two MIS transistors and configured to store data as an irreversible change of transistor characteristics occurring in one of the two MIS transistors, wherein the driver includes at least one nonvolatile memory cell storing count data responsive to a number of times storing of data has been performed with respect to the plurality of nonvolatile memory cells, and is configured to activate one of the word lines indicated by the count data.

    摘要翻译： 非易失性半导体存储器件包括：锁存器，被配置为存储数据，多个字线，被配置为激活多个字线中的一个字线的驱动器;以及耦合到各个字线的多个非易失性存储器单元，每个非易失性存储器件 存储器单元耦合到所述锁存器，以便在激活相应的一条字线时与所述锁存器交换存储的数据，所述非易失性存储器单元中的每一个包括两个MIS晶体管，并且被配置为将数据存储为晶体管特性的不可逆变化， 两个MIS晶体管中的一个，其中驱动器包括至少一个非易失性存储单元，其存储响应于多次数据存储的数量的计数数据，并且被配置为激活多个非易失性存储单元中的一个， 字数由计数数据表示。

    Nonvolatile memory utilizing hot-carrier effect with data reversal function
    4.
    发明授权
    Nonvolatile memory utilizing hot-carrier effect with data reversal function 有权
    使用具有数据反转功能的热载波效应的非易失性存储器

    公开(公告)号：US07483290B2

    公开(公告)日：2009-01-27

    申请号：US11701958

    申请日：2007-02-02

    申请人： Takashi Kikuchi ,  Kenji Noda

    发明人： Takashi Kikuchi ,  Kenji Noda

    IPC分类号： G11C11/00

    CPC分类号： G11C14/00 ,  G11C14/0063

    摘要： A nonvolatile semiconductor memory device includes a control circuit, an inverting circuit, and memory units, each of the memory units including a latch having a first node and a second node, a plate line, a first MIS transistor having one of source/drain nodes coupled to the first node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to a word line, and a second MIS transistor having one of source/drain nodes coupled to the second node of the latch, another one of the source/drain nodes coupled to the plate line, and a gate node coupled to the word line, wherein the control circuit is configured to invert the data latched in the latch by reading the data from the latch, causing the inverting circuit to invert the read data, and writing the inverted data to the latch.

    摘要翻译： 非易失性半导体存储器件包括控制电路，反相电路和存储器单元，每个存储器单元包括具有第一节点和第二节点的锁存器，板线，具有源/漏节点之一的第一MIS晶体管 耦合到锁存器的第一节点，耦合到板线的源极/漏极节点中的另一个以及耦合到字线的栅极节点以及耦合到第二节点的源极/漏极节点之一的第二MIS晶体管 耦合到板线的源/漏节点中的另一个和耦合到字线的栅极节点，其中控制电路被配置为通过从锁存器读取数据来反转锁存在锁存器中的数据， 使反相电路反转读取的数据，并将反相数据写入锁存器。

    Cylinder apparatus
    5.
    发明授权
    Cylinder apparatus 有权
    气缸装置

    公开(公告)号：US08157276B2

    公开(公告)日：2012-04-17

    申请号：US12785671

    申请日：2010-05-24

    申请人： Kenji Noda ,  Yoshiaki Totani

    发明人： Kenji Noda ,  Yoshiaki Totani

    IPC分类号： B60G21/05

    CPC分类号： F16F9/3257 ,  B60G21/0558 ,  F16F9/3242 ,  F16F9/325

    摘要： A piston coupled to a piston rod is inserted in a cylinder, and an outer cylinder is disposed around the cylinder so as to define a reservoir therebetween. A separator tube is disposed around the cylinder so as to define an annular passage therebetween. The piston rod can be locked and unlocked by closing and opening an electromagnetic open/close valve so as to block and allow a flow of hydraulic fluid through a flow passage between the annular passage and the reservoir. The separator tube has a greater thickness. O-rings are disposed so as to provide seals between the separator tube and the cylinder. The separator tube extends to positions such that the ends of the separator tube overlap a base valve and a rod guide, thereby holding the respective ends of the cylinder. Due to this configuration, it is possible to prevent deformation of the cylinder and the separator tube due to an increase in the hydraulic pressure.

    摘要翻译： 联接到活塞杆的活塞插入到气缸中，并且外筒围绕气缸设置以在其间限定一个容器。 分隔管设置在圆筒周围，以便在它们之间限定环形通道。 活塞杆可以通过关闭和打开电磁开关阀而被锁定和解锁，以阻止和允许液压流体流过环形通道和储存器之间的流动通道。 分离管具有更大的厚度。 O形环被设置成在分离器管和气缸之间提供密封。 分离管延伸到使得分离管的端部与基座阀和杆引导件重叠的位置，从而保持气缸的相应端部。 由于这种构造，可以防止由于液压的增加而引起的气缸和分离管的变形。

    MIS-transistor-based nonvolatile memory for multilevel data storage
    8.
    发明授权
    MIS-transistor-based nonvolatile memory for multilevel data storage 有权
    用于多级数据存储的基于MIS晶体管的非易失性存储器

    公开(公告)号：US07733714B2

    公开(公告)日：2010-06-08

    申请号：US12139550

    申请日：2008-06-16

    申请人： Tadahiko Horiuchi ,  Kenji Noda

    发明人： Tadahiko Horiuchi ,  Kenji Noda

    IPC分类号： G11C7/00

    CPC分类号： G11C11/5671 ,  G11C2211/5642 ,  G11C2211/5647

    摘要： A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor to make an upward lingering change in a threshold voltage of the MIS transistor in a first operation in response to data stored in the latch and to make a downward lingering change in the threshold voltage in a second operation in response to data stored in the latch.

    摘要翻译： 存储器电路包括具有第一节点和第二节点的锁存器，用于存储数据，使得第一节点的逻辑电平为第二节点的逻辑电平的倒数，具有门节点的MIS晶体管，第一源/ 漏极节点和第二源极/漏极节点，耦合到锁存器的第一节点的第一源极/漏极节点以及控制电路，被配置为控制MIS晶体管的栅极节点和第二源极/漏极节点向上 响应于存储在锁存器中的数据，在第一操作中MIS晶体管的阈值电压的持续变化，并且响应于存储在锁存器中的数据，在第二操作中使阈值电压下降。

    Polybutylene terephthalate and process for producing thereof
    9.
    发明申请
    Polybutylene terephthalate and process for producing thereof 审中-公开
    聚对苯二甲酸丁二醇酯及其制造方法

    公开(公告)号：US20090054618A1

    公开(公告)日：2009-02-26

    申请号：US11990916

    申请日：2006-08-28

    申请人： Kenji Noda ,  Masanori Yamamoto ,  Shinichiro Matsuzono ,  Toshiyuki Hamano ,  Yoshio Akahane ,  Hidekazu Shouji

    发明人： Kenji Noda ,  Masanori Yamamoto ,  Shinichiro Matsuzono ,  Toshiyuki Hamano ,  Yoshio Akahane ,  Hidekazu Shouji

    IPC分类号： C08G63/183 ,  C08G63/85

    CPC分类号： C08G63/85 ,  C08G63/80

    摘要： An object of the present invention is to provide polybutylene terephthalate which has excellent color tone, hydrolysis resistance, heat stability, transparency and moldability as well as a less content of impurities, can be produced with maintaining its productivity while preventing from generation of tetrahydrofuran as a by-product, and can be suitably applied to films, monofilaments, fibers, electric and electronic parts, automobile parts, etc.In an aspect of the present invention, there is provided a process for continuously producing polybutylene terephthalate from terephthalic acid and 1,4-butanediol in a presence of a catalyst comprising a titanium compound and a compound of at least one metal selected from Group 1 and Group 2 of the Periodic Table, which process satisfies such the following requirements (a) to (c) that: (a) an oligomer is obtained by conducting a continuously esterification reaction of terephthalic acid and 1,4-butanediol in the presence of titanium catalyst in an amount of not more than 460 μmol as a titanium atom based on 1 mol of terephthalic acid unit; (b) polycondensation reaction of the said oligomer is continuously conducted in the presence of compound of at least one metal selected from Group 1 and Group 2 of the Periodic Table as the catalyst in an amount of not more than 450 μmol as the metal atom based on 1 mol of terephthalic acid unit; and (c) the said compound of at least one metal may be added to a stage before obtaining an oligomer having esterification conversion of not less than 90% in an amount of not more than 300 μmol as the metal atom based on 1 mol of terephthalic acid unit, and the said compound of at least one metal may be added to a stage on or after obtaining an oligomer having esterification conversion of not less than 90% in an amount of not less than 10 μmol as the metal atom based on 1 mol of terephthalic acid unit.

    摘要翻译： 本发明的目的是提供具有优异色调，耐水解性，热稳定性，透明性和成型性以及较少杂质含量的聚对苯二甲酸丁二醇酯，同时保持其生产率，同时防止产生四氢呋喃作为 副产物，可适用于薄膜，单丝，纤维，电气电子部件，汽车部件等。在本发明的一个方面，提供了一种从对苯二甲酸和1， 在包含钛化合物和选自元素周期表第1族和第2族中的至少一种金属的化合物的催化剂存在下，该方法满足以下要求（a）至（c）：（ a）通过在钛催化剂的存在下进行对苯二甲酸和1,4-丁二醇的连续酯化反应获得低聚物 相对于1摩尔对苯二甲酸单元，钛原子为460摩尔以下的量; （b）所述低聚物的缩聚反应在作为催化剂的至少一种选自元素周期表第1族和第2族的金属的化合物存在下连续进行，其金属原子数不超过450μmol 在1mol对苯二甲酸单元上; 和（c）所述至少一种金属的化合物可以在获得具有不低于90％的酯化转化率的低聚物之后的阶段中加入到作为金属原子的不超过300μmol的量，基于1mol对苯二甲酸 酸单元，并且所述至少一种金属的化合物可以在获得基于1摩尔的金属原子的不少于10摩尔的酯化转化率为90％以上的低聚物或其后添加 的对苯二甲酸单元。

    Nonvolatile memory device with test mechanism
    10.
    发明授权
    Nonvolatile memory device with test mechanism 有权
    具有测试机制的非易失性存储器件

    公开(公告)号：US07414903B2

    公开(公告)日：2008-08-19

    申请号：US11413987

    申请日：2006-04-28

    申请人： Kenji Noda

    发明人： Kenji Noda

    IPC分类号： G11C29/00

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C29/50016

    摘要： A nonvolatile semiconductor memory device includes a memory cell having a MIS transistor configured to experience an irreversible change in transistor characteristics thereof to store data as the irreversible change, the MIS transistor having a gate node coupled to a word selecting line and a source/drain node coupled to a bit line, and the MIS transistor becoming conductive in response to a first state of the word selecting line and becoming nonconductive in response to a second state of the word selecting line, and a test circuit coupled to the bit line to sense a current running through the MIS transistor, the test circuit configured to indicate error in response to either a detection of presence of the current when the word selecting line is in the second state or a detection of absence of the current when the word selecting line is in the first state.

    摘要翻译： 非易失性半导体存储器件包括具有MIS晶体管的存储单元，其被配置为经历其晶体管特性的不可逆变化以将数据存储为不可逆变化，所述MIS晶体管具有耦合到字选择线和源极/漏极节点 耦合到位线，并且所述MIS晶体管响应于所述字选择线的第一状态变为导通，并且响应于所述字选择线的第二状态变为不导通，以及耦合到所述位线以感测 电流流过MIS晶体管，测试电路被配置为响应于当字选择线处于第二状态时检测到电流的存在或者当字选择线处于第二状态时检测到电流的错误 第一个状态。